mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 12:06:42 +07:00
36c46ca4f3
Add valid patch size for family 16h processors. [ hpa: promoting to urgent/stable since it is hw enabling and trivial ] Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com> Acked-by: Andreas Herrmann <herrmann.der.user@googlemail.com> Link: http://lkml.kernel.org/r/1353004910-2204-1-git-send-email-boris.ostrovsky@amd.com Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Cc: <stable@vger.kernel.org>
494 lines
11 KiB
C
494 lines
11 KiB
C
/*
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* AMD CPU Microcode Update Driver for Linux
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* Copyright (C) 2008-2011 Advanced Micro Devices Inc.
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*
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* Author: Peter Oruba <peter.oruba@amd.com>
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*
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* Based on work by:
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* Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
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*
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* Maintainers:
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* Andreas Herrmann <herrmann.der.user@googlemail.com>
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* Borislav Petkov <bp@alien8.de>
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*
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* This driver allows to upgrade microcode on F10h AMD
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* CPUs and later.
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*
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* Licensed under the terms of the GNU General Public
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* License version 2. See file COPYING for details.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/firmware.h>
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#include <linux/pci_ids.h>
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#include <linux/uaccess.h>
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#include <linux/vmalloc.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <asm/microcode.h>
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#include <asm/processor.h>
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#include <asm/msr.h>
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MODULE_DESCRIPTION("AMD Microcode Update Driver");
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MODULE_AUTHOR("Peter Oruba");
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MODULE_LICENSE("GPL v2");
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#define UCODE_MAGIC 0x00414d44
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#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
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#define UCODE_UCODE_TYPE 0x00000001
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struct equiv_cpu_entry {
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u32 installed_cpu;
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u32 fixed_errata_mask;
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u32 fixed_errata_compare;
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u16 equiv_cpu;
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u16 res;
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} __attribute__((packed));
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struct microcode_header_amd {
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u32 data_code;
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u32 patch_id;
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u16 mc_patch_data_id;
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u8 mc_patch_data_len;
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u8 init_flag;
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u32 mc_patch_data_checksum;
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u32 nb_dev_id;
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u32 sb_dev_id;
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u16 processor_rev_id;
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u8 nb_rev_id;
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u8 sb_rev_id;
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u8 bios_api_rev;
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u8 reserved1[3];
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u32 match_reg[8];
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} __attribute__((packed));
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struct microcode_amd {
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struct microcode_header_amd hdr;
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unsigned int mpb[0];
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};
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#define SECTION_HDR_SIZE 8
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#define CONTAINER_HDR_SZ 12
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static struct equiv_cpu_entry *equiv_cpu_table;
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struct ucode_patch {
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struct list_head plist;
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void *data;
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u32 patch_id;
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u16 equiv_cpu;
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};
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static LIST_HEAD(pcache);
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static u16 find_equiv_id(unsigned int cpu)
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{
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struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
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int i = 0;
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if (!equiv_cpu_table)
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return 0;
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while (equiv_cpu_table[i].installed_cpu != 0) {
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if (uci->cpu_sig.sig == equiv_cpu_table[i].installed_cpu)
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return equiv_cpu_table[i].equiv_cpu;
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i++;
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}
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return 0;
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}
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static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu)
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{
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int i = 0;
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BUG_ON(!equiv_cpu_table);
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while (equiv_cpu_table[i].equiv_cpu != 0) {
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if (equiv_cpu == equiv_cpu_table[i].equiv_cpu)
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return equiv_cpu_table[i].installed_cpu;
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i++;
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}
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return 0;
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}
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/*
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* a small, trivial cache of per-family ucode patches
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*/
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static struct ucode_patch *cache_find_patch(u16 equiv_cpu)
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{
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struct ucode_patch *p;
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list_for_each_entry(p, &pcache, plist)
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if (p->equiv_cpu == equiv_cpu)
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return p;
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return NULL;
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}
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static void update_cache(struct ucode_patch *new_patch)
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{
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struct ucode_patch *p;
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list_for_each_entry(p, &pcache, plist) {
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if (p->equiv_cpu == new_patch->equiv_cpu) {
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if (p->patch_id >= new_patch->patch_id)
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/* we already have the latest patch */
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return;
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list_replace(&p->plist, &new_patch->plist);
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kfree(p->data);
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kfree(p);
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return;
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}
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}
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/* no patch found, add it */
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list_add_tail(&new_patch->plist, &pcache);
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}
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static void free_cache(void)
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{
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struct ucode_patch *p, *tmp;
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list_for_each_entry_safe(p, tmp, &pcache, plist) {
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__list_del(p->plist.prev, p->plist.next);
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kfree(p->data);
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kfree(p);
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}
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}
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static struct ucode_patch *find_patch(unsigned int cpu)
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{
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u16 equiv_id;
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equiv_id = find_equiv_id(cpu);
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if (!equiv_id)
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return NULL;
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return cache_find_patch(equiv_id);
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}
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static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
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{
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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csig->sig = cpuid_eax(0x00000001);
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csig->rev = c->microcode;
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pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
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return 0;
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}
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static unsigned int verify_patch_size(int cpu, u32 patch_size,
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unsigned int size)
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{
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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u32 max_size;
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#define F1XH_MPB_MAX_SIZE 2048
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#define F14H_MPB_MAX_SIZE 1824
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#define F15H_MPB_MAX_SIZE 4096
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#define F16H_MPB_MAX_SIZE 3458
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switch (c->x86) {
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case 0x14:
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max_size = F14H_MPB_MAX_SIZE;
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break;
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case 0x15:
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max_size = F15H_MPB_MAX_SIZE;
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break;
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case 0x16:
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max_size = F16H_MPB_MAX_SIZE;
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break;
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default:
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max_size = F1XH_MPB_MAX_SIZE;
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break;
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}
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if (patch_size > min_t(u32, size, max_size)) {
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pr_err("patch size mismatch\n");
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return 0;
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}
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return patch_size;
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}
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static int apply_microcode_amd(int cpu)
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{
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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struct microcode_amd *mc_amd;
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struct ucode_cpu_info *uci;
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struct ucode_patch *p;
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u32 rev, dummy;
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BUG_ON(raw_smp_processor_id() != cpu);
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uci = ucode_cpu_info + cpu;
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p = find_patch(cpu);
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if (!p)
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return 0;
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mc_amd = p->data;
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uci->mc = p->data;
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rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
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/* need to apply patch? */
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if (rev >= mc_amd->hdr.patch_id) {
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c->microcode = rev;
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return 0;
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}
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wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
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/* verify patch application was successful */
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rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
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if (rev != mc_amd->hdr.patch_id) {
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pr_err("CPU%d: update failed for patch_level=0x%08x\n",
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cpu, mc_amd->hdr.patch_id);
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return -1;
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}
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pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
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uci->cpu_sig.rev = rev;
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c->microcode = rev;
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return 0;
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}
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static int install_equiv_cpu_table(const u8 *buf)
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{
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unsigned int *ibuf = (unsigned int *)buf;
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unsigned int type = ibuf[1];
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unsigned int size = ibuf[2];
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if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
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pr_err("empty section/"
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"invalid type field in container file section header\n");
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return -EINVAL;
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}
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equiv_cpu_table = vmalloc(size);
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if (!equiv_cpu_table) {
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pr_err("failed to allocate equivalent CPU table\n");
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return -ENOMEM;
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}
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memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);
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/* add header length */
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return size + CONTAINER_HDR_SZ;
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}
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static void free_equiv_cpu_table(void)
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{
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vfree(equiv_cpu_table);
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equiv_cpu_table = NULL;
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}
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static void cleanup(void)
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{
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free_equiv_cpu_table();
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free_cache();
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}
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/*
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* We return the current size even if some of the checks failed so that
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* we can skip over the next patch. If we return a negative value, we
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* signal a grave error like a memory allocation has failed and the
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* driver cannot continue functioning normally. In such cases, we tear
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* down everything we've used up so far and exit.
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*/
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static int verify_and_add_patch(unsigned int cpu, u8 *fw, unsigned int leftover)
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{
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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struct microcode_header_amd *mc_hdr;
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struct ucode_patch *patch;
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unsigned int patch_size, crnt_size, ret;
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u32 proc_fam;
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u16 proc_id;
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patch_size = *(u32 *)(fw + 4);
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crnt_size = patch_size + SECTION_HDR_SIZE;
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mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
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proc_id = mc_hdr->processor_rev_id;
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proc_fam = find_cpu_family_by_equiv_cpu(proc_id);
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if (!proc_fam) {
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pr_err("No patch family for equiv ID: 0x%04x\n", proc_id);
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return crnt_size;
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}
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/* check if patch is for the current family */
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proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff);
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if (proc_fam != c->x86)
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return crnt_size;
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if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
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pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n",
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mc_hdr->patch_id);
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return crnt_size;
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}
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ret = verify_patch_size(cpu, patch_size, leftover);
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if (!ret) {
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pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id);
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return crnt_size;
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}
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patch = kzalloc(sizeof(*patch), GFP_KERNEL);
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if (!patch) {
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pr_err("Patch allocation failure.\n");
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return -EINVAL;
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}
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patch->data = kzalloc(patch_size, GFP_KERNEL);
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if (!patch->data) {
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pr_err("Patch data allocation failure.\n");
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kfree(patch);
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return -EINVAL;
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}
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/* All looks ok, copy patch... */
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memcpy(patch->data, fw + SECTION_HDR_SIZE, patch_size);
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INIT_LIST_HEAD(&patch->plist);
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patch->patch_id = mc_hdr->patch_id;
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patch->equiv_cpu = proc_id;
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/* ... and add to cache. */
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update_cache(patch);
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return crnt_size;
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}
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static enum ucode_state load_microcode_amd(int cpu, const u8 *data, size_t size)
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{
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enum ucode_state ret = UCODE_ERROR;
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unsigned int leftover;
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u8 *fw = (u8 *)data;
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int crnt_size = 0;
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int offset;
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offset = install_equiv_cpu_table(data);
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if (offset < 0) {
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pr_err("failed to create equivalent cpu table\n");
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return ret;
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}
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fw += offset;
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leftover = size - offset;
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if (*(u32 *)fw != UCODE_UCODE_TYPE) {
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pr_err("invalid type field in container file section header\n");
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free_equiv_cpu_table();
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return ret;
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}
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while (leftover) {
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crnt_size = verify_and_add_patch(cpu, fw, leftover);
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if (crnt_size < 0)
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return ret;
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fw += crnt_size;
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leftover -= crnt_size;
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}
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return UCODE_OK;
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}
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/*
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* AMD microcode firmware naming convention, up to family 15h they are in
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* the legacy file:
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*
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* amd-ucode/microcode_amd.bin
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*
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* This legacy file is always smaller than 2K in size.
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*
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* Beginning with family 15h, they are in family-specific firmware files:
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*
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* amd-ucode/microcode_amd_fam15h.bin
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* amd-ucode/microcode_amd_fam16h.bin
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* ...
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*
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* These might be larger than 2K.
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*/
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static enum ucode_state request_microcode_amd(int cpu, struct device *device,
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bool refresh_fw)
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{
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char fw_name[36] = "amd-ucode/microcode_amd.bin";
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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enum ucode_state ret = UCODE_NFOUND;
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const struct firmware *fw;
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/* reload ucode container only on the boot cpu */
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if (!refresh_fw || c->cpu_index != boot_cpu_data.cpu_index)
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return UCODE_OK;
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if (c->x86 >= 0x15)
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snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
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if (request_firmware(&fw, (const char *)fw_name, device)) {
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pr_err("failed to load file %s\n", fw_name);
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goto out;
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}
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ret = UCODE_ERROR;
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if (*(u32 *)fw->data != UCODE_MAGIC) {
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pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data);
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goto fw_release;
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}
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/* free old equiv table */
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free_equiv_cpu_table();
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ret = load_microcode_amd(cpu, fw->data, fw->size);
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if (ret != UCODE_OK)
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cleanup();
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fw_release:
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release_firmware(fw);
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out:
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return ret;
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}
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static enum ucode_state
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request_microcode_user(int cpu, const void __user *buf, size_t size)
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{
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return UCODE_ERROR;
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}
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static void microcode_fini_cpu_amd(int cpu)
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{
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struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
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uci->mc = NULL;
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}
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static struct microcode_ops microcode_amd_ops = {
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.request_microcode_user = request_microcode_user,
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.request_microcode_fw = request_microcode_amd,
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.collect_cpu_info = collect_cpu_info_amd,
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.apply_microcode = apply_microcode_amd,
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.microcode_fini_cpu = microcode_fini_cpu_amd,
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};
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struct microcode_ops * __init init_amd_microcode(void)
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{
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struct cpuinfo_x86 *c = &cpu_data(0);
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if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
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pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
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return NULL;
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}
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return µcode_amd_ops;
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}
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void __exit exit_amd_microcode(void)
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{
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cleanup();
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}
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