mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 13:25:12 +07:00
dec1fbbc1d
* Spelling * http to https updates NAND core changes: * Drop useless 'depends on' in Kconfig * Add an extra level in the Kconfig hierarchy * Trivial spellings * Dynamic allocation of the interface configurations * Dropping the default ONFI timing mode * Various cleanup (types, structures, naming, comments) * Hide the chip->data_interface indirection * Add the generic rb-gpios property * Add the ->choose_interface_config() hook * Introduce nand_choose_best_sdr_timings() * Use default values for tPROG_max and tBERS_max * Avoid redefining tR_max and tCCS_min * Add a helper to find the closest ONFI mode * bcm63xx MTD parsers: simplify CFE detection Raw NAND controller drivers changes: * fsl-upm: Deprecation of specific DT properties * fsl_upm: Driver rework and cleanup in favor of ->exec_op() * Ingenic: Cleanup ARRAY_SIZE() vs sizeof() use * brcmnand: ECC error handling on EDU transfers * brcmnand: Don't default to EDU transfers * qcom: Set BAM mode only if not set already * qcom: Avoid write to unavailable register * gpio: Driver rework in favor of ->exec_op() * tango: ->exec_op() conversion * mtk: ->exec_op() conversion Raw NAND chip drivers changes: * toshiba: Implement ->choose_interface_config() for TH58NVG2S3HBAI4 * toshiba: Implement ->choose_interface_config() for TC58NVG0S3E * toshiba: Implement ->choose_interface_config() for TC58TEG5DCLTA00 * hynix: Implement ->choose_interface_config() for H27UCG8T2ATR-BC SPI NOR core changes: * Disable Quad Mode in spi_nor_restore(). * Don't abort BFPT parsing when QER reserved value is used. * Add support/update capabilities for few flashes. * Drop s70fl01gs flash: it does not support RDSR(05h) which is critical for erase/write. * Merge the SPIMEM DTR bits in spi-nor/next to avoid conflicts during the release cycle. SPI NOR controller drivers changes: * Move the cadence-quadspi driver to spi-mem. The series was taken through the SPI tree. Merge it also in spi-nor/next to avoid conflicts during the release cycle. * intel-spi: - Add new PCI IDs. - Ignore the Write Disable command, the controller doesn't support it. - Fix performance regression. -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEE9HuaYnbmDhq/XIDIJWrqGEe9VoQFAl8vJtMACgkQJWrqGEe9 VoRdGAf/Y5m5BwmLilkEYpffyxi7dVR6XOKPLU5EJXkS3dPvH9398zchbHOdedCZ OzJIfh6Iv+qbkgS2g0lAAT+SAfOfG9plubvSdkjrHXl4eZXRnR/49RF5LAEju7sz Uw1HdRcawyEi5uI9yYS0tCeVMIUJq+5x7VibH+82yOIdSPc60c7FDc5ih/nVKj/a Pn9LOzGzkdndcE1b3FcF2Uk/T1YOJx3Yt5ngALlPpJxaDZmQSHtYPuuz8DfUbamf uj3CkpqYRyT18CzuFvtuba6LyF+donXNJgvl6ivW7dlRSPzSMnDQu7J5bpNhUfcd p/ZdzX1Jxle4theDm0J9ALsSSM5g2w== =RiY8 -----END PGP SIGNATURE----- Merge tag 'mtd/for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull mtd updates from Miquel Raynal: "MTD core changes: - Spelling - http to https updates NAND core changes: - Drop useless 'depends on' in Kconfig - Add an extra level in the Kconfig hierarchy - Trivial spellings - Dynamic allocation of the interface configurations - Dropping the default ONFI timing mode - Various cleanup (types, structures, naming, comments) - Hide the chip->data_interface indirection - Add the generic rb-gpios property - Add the ->choose_interface_config() hook - Introduce nand_choose_best_sdr_timings() - Use default values for tPROG_max and tBERS_max - Avoid redefining tR_max and tCCS_min - Add a helper to find the closest ONFI mode - bcm63xx MTD parsers: simplify CFE detection Raw NAND controller drivers changes: - fsl-upm: Deprecation of specific DT properties - fsl_upm: Driver rework and cleanup in favor of ->exec_op() - Ingenic: Cleanup ARRAY_SIZE() vs sizeof() use - brcmnand: ECC error handling on EDU transfers - brcmnand: Don't default to EDU transfers - qcom: Set BAM mode only if not set already - qcom: Avoid write to unavailable register - gpio: Driver rework in favor of ->exec_op() - tango: ->exec_op() conversion - mtk: ->exec_op() conversion Raw NAND chip drivers changes: - toshiba: Implement ->choose_interface_config() for TH58NVG2S3HBAI4, TC58NVG0S3E, and TC58TEG5DCLTA00 - hynix: Implement ->choose_interface_config() for H27UCG8T2ATR-BC SPI NOR core changes: - Disable Quad Mode in spi_nor_restore(). - Don't abort BFPT parsing when QER reserved value is used. - Add support/update capabilities for few flashes. - Drop s70fl01gs flash: it does not support RDSR(05h) which is critical for erase/write. - Merge the SPIMEM DTR bits in spi-nor/next to avoid conflicts during the release cycle. SPI NOR controller drivers changes: - Move the cadence-quadspi driver to spi-mem. The series was taken through the SPI tree. Merge it also in spi-nor/next to avoid conflicts during the release cycle. - intel-spi: - Add new PCI IDs. - Ignore the Write Disable command, the controller doesn't support it. - Fix performance regression" * tag 'mtd/for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (79 commits) MTD: pfow.h: drop a duplicated word MTD: mtd-abi.h: drop a duplicated word mtd: rawnand: omap_elm: Replace HTTP links with HTTPS ones mtd: Replace HTTP links with HTTPS ones mtd: hyperbus: Replace HTTP links with HTTPS ones mtd: revert "spi-nor: intel: provide a range for poll_timout" mtd: spi-nor: update read capabilities for w25q64 and s25fl064k mtd: spi-nor: micron: Add SPI_NOR_DUAL_READ flag on mt25qu02g mtd: spi-nor: macronix: Add support for mx66u2g45g mtd: spi-nor: intel-spi: Simulate WRDI command mtd: spi-nor: Disable the flash quad mode in spi_nor_restore() mtd: spi-nor: Add capability to disable flash quad mode mtd: spi-nor: spansion: Remove s70fl01gs from flash_info mtd: spi-nor: sfdp: do not make invalid quad enable fatal dt-bindings: mtd: fsl-upm-nand: Deprecate chip-delay and fsl, upm-wait-flags mtd: rawnand: stm32_fmc2: get resources from parent node mtd: rawnand: stm32_fmc2: use regmap APIs memory: stm32-fmc2-ebi: add STM32 FMC2 EBI controller driver dt-bindings: memory-controller: add STM32 FMC2 EBI controller documentation dt-bindings: mtd: update STM32 FMC2 NAND controller documentation ...
205 lines
6.9 KiB
Plaintext
205 lines
6.9 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
|
|
#
|
|
# Memory devices
|
|
#
|
|
|
|
menuconfig MEMORY
|
|
bool "Memory Controller drivers"
|
|
help
|
|
This option allows to enable specific memory controller drivers,
|
|
useful mostly on embedded systems. These could be controllers
|
|
for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features
|
|
vary from memory tuning and frequency scaling to enabling
|
|
access to attached peripherals through memory bus.
|
|
|
|
if MEMORY
|
|
|
|
config DDR
|
|
bool
|
|
help
|
|
Data from JEDEC specs for DDR SDRAM memories,
|
|
particularly the AC timing parameters and addressing
|
|
information. This data is useful for drivers handling
|
|
DDR SDRAM controllers.
|
|
|
|
config ARM_PL172_MPMC
|
|
tristate "ARM PL172 MPMC driver"
|
|
depends on ARM_AMBA && OF
|
|
help
|
|
This selects the ARM PrimeCell PL172 MultiPort Memory Controller.
|
|
If you have an embedded system with an AMBA bus and a PL172
|
|
controller, say Y or M here.
|
|
|
|
config ATMEL_SDRAMC
|
|
bool "Atmel (Multi-port DDR-)SDRAM Controller"
|
|
default y
|
|
depends on ARCH_AT91 && OF
|
|
help
|
|
This driver is for Atmel SDRAM Controller or Atmel Multi-port
|
|
DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
|
|
Starting with the at91sam9g45, this controller supports SDR, DDR and
|
|
LP-DDR memories.
|
|
|
|
config ATMEL_EBI
|
|
bool "Atmel EBI driver"
|
|
default y
|
|
depends on ARCH_AT91 && OF
|
|
select MFD_SYSCON
|
|
select MFD_ATMEL_SMC
|
|
help
|
|
Driver for Atmel EBI controller.
|
|
Used to configure the EBI (external bus interface) when the device-
|
|
tree is used. This bus supports NANDs, external ethernet controller,
|
|
SRAMs, ATA devices, etc.
|
|
|
|
config BT1_L2_CTL
|
|
bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
|
|
depends on MIPS_BAIKAL_T1 || COMPILE_TEST
|
|
select MFD_SYSCON
|
|
help
|
|
Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
|
|
resides Coherency Manager v2 with embedded 1MB L2-cache. It's
|
|
possible to tune the L2 cache performance up by setting the data,
|
|
tags and way-select latencies of RAM access. This driver provides a
|
|
dt properties-based and sysfs interface for it.
|
|
|
|
config TI_AEMIF
|
|
tristate "Texas Instruments AEMIF driver"
|
|
depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF
|
|
help
|
|
This driver is for the AEMIF module available in Texas Instruments
|
|
SoCs. AEMIF stands for Asynchronous External Memory Interface and
|
|
is intended to provide a glue-less interface to a variety of
|
|
asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
|
|
of 256M bytes of any of these memories can be accessed at a given
|
|
time via four chip selects with 64M byte access per chip select.
|
|
|
|
config TI_EMIF
|
|
tristate "Texas Instruments EMIF driver"
|
|
depends on ARCH_OMAP2PLUS
|
|
select DDR
|
|
help
|
|
This driver is for the EMIF module available in Texas Instruments
|
|
SoCs. EMIF is an SDRAM controller that, based on its revision,
|
|
supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
|
|
This driver takes care of only LPDDR2 memories presently. The
|
|
functions of the driver includes re-configuring AC timing
|
|
parameters and other settings during frequency, voltage and
|
|
temperature changes
|
|
|
|
config OMAP_GPMC
|
|
bool
|
|
select GPIOLIB
|
|
help
|
|
This driver is for the General Purpose Memory Controller (GPMC)
|
|
present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows
|
|
interfacing to a variety of asynchronous as well as synchronous
|
|
memory drives like NOR, NAND, OneNAND, SRAM.
|
|
|
|
config OMAP_GPMC_DEBUG
|
|
bool "Enable GPMC debug output and skip reset of GPMC during init"
|
|
depends on OMAP_GPMC
|
|
help
|
|
Enables verbose debugging mostly to decode the bootloader provided
|
|
timings. To preserve the bootloader provided timings, the reset
|
|
of GPMC is skipped during init. Enable this during development to
|
|
configure devices connected to the GPMC bus.
|
|
|
|
NOTE: In addition to matching the register setup with the bootloader
|
|
you also need to match the GPMC FCLK frequency used by the
|
|
bootloader or else the GPMC timings won't be identical with the
|
|
bootloader timings.
|
|
|
|
config TI_EMIF_SRAM
|
|
tristate "Texas Instruments EMIF SRAM driver"
|
|
depends on (SOC_AM33XX || SOC_AM43XX) && SRAM
|
|
help
|
|
This driver is for the EMIF module available on Texas Instruments
|
|
AM33XX and AM43XX SoCs and is required for PM. Certain parts of
|
|
the EMIF PM code must run from on-chip SRAM late in the suspend
|
|
sequence so this driver provides several relocatable PM functions
|
|
for the SoC PM code to use.
|
|
|
|
config MVEBU_DEVBUS
|
|
bool "Marvell EBU Device Bus Controller"
|
|
default y
|
|
depends on PLAT_ORION && OF
|
|
help
|
|
This driver is for the Device Bus controller available in some
|
|
Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
|
|
Armada 370 and Armada XP. This controller allows to handle flash
|
|
devices such as NOR, NAND, SRAM, and FPGA.
|
|
|
|
config FSL_CORENET_CF
|
|
tristate "Freescale CoreNet Error Reporting"
|
|
depends on FSL_SOC_BOOKE
|
|
help
|
|
Say Y for reporting of errors from the Freescale CoreNet
|
|
Coherency Fabric. Errors reported include accesses to
|
|
physical addresses that mapped by no local access window
|
|
(LAW) or an invalid LAW, as well as bad cache state that
|
|
represents a coherency violation.
|
|
|
|
config FSL_IFC
|
|
bool
|
|
depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A || COMPILE_TEST
|
|
depends on HAS_IOMEM
|
|
|
|
config JZ4780_NEMC
|
|
bool "Ingenic JZ4780 SoC NEMC driver"
|
|
depends on MIPS || COMPILE_TEST
|
|
depends on HAS_IOMEM && OF
|
|
help
|
|
This driver is for the NAND/External Memory Controller (NEMC) in
|
|
the Ingenic JZ4780. This controller is used to handle external
|
|
memory devices such as NAND and SRAM.
|
|
|
|
config MTK_SMI
|
|
bool
|
|
depends on ARCH_MEDIATEK || COMPILE_TEST
|
|
help
|
|
This driver is for the Memory Controller module in MediaTek SoCs,
|
|
mainly help enable/disable iommu and control the power domain and
|
|
clocks for each local arbiter.
|
|
|
|
config DA8XX_DDRCTL
|
|
bool "Texas Instruments da8xx DDR2/mDDR driver"
|
|
depends on ARCH_DAVINCI_DA8XX
|
|
help
|
|
This driver is for the DDR2/mDDR Memory Controller present on
|
|
Texas Instruments da8xx SoCs. It's used to tweak various memory
|
|
controller configuration options.
|
|
|
|
config PL353_SMC
|
|
tristate "ARM PL35X Static Memory Controller(SMC) driver"
|
|
default y
|
|
depends on ARM
|
|
depends on ARM_AMBA
|
|
help
|
|
This driver is for the ARM PL351/PL353 Static Memory
|
|
Controller(SMC) module.
|
|
|
|
config RENESAS_RPCIF
|
|
tristate "Renesas RPC-IF driver"
|
|
depends on ARCH_RENESAS
|
|
select REGMAP_MMIO
|
|
help
|
|
This supports Renesas R-Car Gen3 RPC-IF which provides either SPI
|
|
host or HyperFlash. You'll have to select individual components
|
|
under the corresponding menu.
|
|
|
|
config STM32_FMC2_EBI
|
|
tristate "Support for FMC2 External Bus Interface on STM32MP SoCs"
|
|
depends on MACH_STM32MP157 || COMPILE_TEST
|
|
select MFD_SYSCON
|
|
help
|
|
Select this option to enable the STM32 FMC2 External Bus Interface
|
|
controller. This driver configures the transactions with external
|
|
devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on
|
|
SOCs containing the FMC2 External Bus Interface.
|
|
|
|
source "drivers/memory/samsung/Kconfig"
|
|
source "drivers/memory/tegra/Kconfig"
|
|
|
|
endif
|