mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 13:05:10 +07:00
d457ef358f
This supports power-gated idle on secondary CPUs for Tegra30. The secondary CPUs can go into powered-down state independently. When CPU goes into this state, it saves it's contexts and puts itself to flow controlled WFI state. After that, it will been power gated. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
60 lines
1.6 KiB
C
60 lines
1.6 KiB
C
/*
|
|
* arch/arm/mach-tegra/reset.h
|
|
*
|
|
* CPU reset dispatcher.
|
|
*
|
|
* Copyright (c) 2011, NVIDIA Corporation.
|
|
*
|
|
* This software is licensed under the terms of the GNU General Public
|
|
* License version 2, as published by the Free Software Foundation, and
|
|
* may be copied, distributed, and modified under those terms.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
*/
|
|
|
|
#ifndef __MACH_TEGRA_RESET_H
|
|
#define __MACH_TEGRA_RESET_H
|
|
|
|
#define TEGRA_RESET_MASK_PRESENT 0
|
|
#define TEGRA_RESET_MASK_LP1 1
|
|
#define TEGRA_RESET_MASK_LP2 2
|
|
#define TEGRA_RESET_STARTUP_SECONDARY 3
|
|
#define TEGRA_RESET_STARTUP_LP2 4
|
|
#define TEGRA_RESET_STARTUP_LP1 5
|
|
#define TEGRA_RESET_DATA_SIZE 6
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
#include "irammap.h"
|
|
|
|
extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
|
|
|
|
void __tegra_cpu_reset_handler_start(void);
|
|
void __tegra_cpu_reset_handler(void);
|
|
void __tegra_cpu_reset_handler_end(void);
|
|
void tegra_secondary_startup(void);
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
#define tegra_cpu_lp2_mask \
|
|
(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
|
|
((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
|
|
(u32)__tegra_cpu_reset_handler_start)))
|
|
#endif
|
|
|
|
#define tegra_cpu_reset_handler_offset \
|
|
((u32)__tegra_cpu_reset_handler - \
|
|
(u32)__tegra_cpu_reset_handler_start)
|
|
|
|
#define tegra_cpu_reset_handler_size \
|
|
(__tegra_cpu_reset_handler_end - \
|
|
__tegra_cpu_reset_handler_start)
|
|
|
|
void __init tegra_cpu_reset_handler_init(void);
|
|
|
|
#endif
|
|
#endif
|