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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c620f7bd0b
Mostly just incremental improvements here: - Introduce AT_HWCAP2 for advertising CPU features to userspace - Expose SVE2 availability to userspace - Support for "data cache clean to point of deep persistence" (DC PODP) - Honour "mitigations=off" on the cmdline and advertise status via sysfs - CPU timer erratum workaround (Neoverse-N1 #1188873) - Introduce perf PMU driver for the SMMUv3 performance counters - Add config option to disable the kuser helpers page for AArch32 tasks - Futex modifications to ensure liveness under contention - Rework debug exception handling to seperate kernel and user handlers - Non-critical fixes and cleanup -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEPxTL6PPUbjXGY88ct6xw3ITBYzQFAlzMFGgACgkQt6xw3ITB YzTicAf/TX1h1+ecbx4WJAa4qeiOCPoNpG9efldQumqJhKL44MR5bkhuShna5mwE ptm5qUXkZCxLTjzssZKnbdbgwa3t+emW8Of3D91IfI9akiZbMoDx5FGgcNbqjazb RLrhOFHwgontA38yppZN+DrL+sXbvif/CVELdHahkEx6KepSGaS2lmPXRmz/W56v 4yIRy/zxc3Dhjgfm3wKh72nBwoZdLiIc4mchd5pthNlR9E2idrYkQegG1C+gA00r o8uZRVOWgoh7H+QJE+xLUc8PaNCg8xqRRXOuZYg9GOz6hh7zSWhm+f1nRz9S2tIR gIgsCHNqoO2I3E1uJpAQXDGtt2kFhA== =ulpJ -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Will Deacon: "Mostly just incremental improvements here: - Introduce AT_HWCAP2 for advertising CPU features to userspace - Expose SVE2 availability to userspace - Support for "data cache clean to point of deep persistence" (DC PODP) - Honour "mitigations=off" on the cmdline and advertise status via sysfs - CPU timer erratum workaround (Neoverse-N1 #1188873) - Introduce perf PMU driver for the SMMUv3 performance counters - Add config option to disable the kuser helpers page for AArch32 tasks - Futex modifications to ensure liveness under contention - Rework debug exception handling to seperate kernel and user handlers - Non-critical fixes and cleanup" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (92 commits) Documentation: Add ARM64 to kernel-parameters.rst arm64/speculation: Support 'mitigations=' cmdline option arm64: ssbs: Don't treat CPUs with SSBS as unaffected by SSB arm64: enable generic CPU vulnerabilites support arm64: add sysfs vulnerability show for speculative store bypass arm64: Fix size of __early_cpu_boot_status clocksource/arm_arch_timer: Use arch_timer_read_counter to access stable counters clocksource/arm_arch_timer: Remove use of workaround static key clocksource/arm_arch_timer: Drop use of static key in arch_timer_reg_read_stable clocksource/arm_arch_timer: Direcly assign set_next_event workaround arm64: Use arch_timer_read_counter instead of arch_counter_get_cntvct watchdog/sbsa: Use arch_timer_read_counter instead of arch_counter_get_cntvct ARM: vdso: Remove dependency with the arch_timer driver internals arm64: Apply ARM64_ERRATUM_1188873 to Neoverse-N1 arm64: Add part number for Neoverse N1 arm64: Make ARM64_ERRATUM_1188873 depend on COMPAT arm64: Restrict ARM64_ERRATUM_1188873 mitigation to AArch32 arm64: mm: Remove pte_unmap_nested() arm64: Fix compiler warning from pte_unmap() with -Wunused-but-set-variable arm64: compat: Reduce address limit for 64K pages ...
145 lines
3.4 KiB
C
145 lines
3.4 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_FUTEX_H
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#define __ASM_FUTEX_H
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#ifdef __KERNEL__
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#include <linux/futex.h>
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#include <linux/uaccess.h>
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#include <asm/errno.h>
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#define FUTEX_MAX_LOOPS 128 /* What's the largest number you can think of? */
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#define __futex_atomic_op(insn, ret, oldval, uaddr, tmp, oparg) \
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do { \
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unsigned int loops = FUTEX_MAX_LOOPS; \
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\
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uaccess_enable(); \
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asm volatile( \
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" prfm pstl1strm, %2\n" \
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"1: ldxr %w1, %2\n" \
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insn "\n" \
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"2: stlxr %w0, %w3, %2\n" \
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" cbz %w0, 3f\n" \
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" sub %w4, %w4, %w0\n" \
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" cbnz %w4, 1b\n" \
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" mov %w0, %w7\n" \
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"3:\n" \
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" dmb ish\n" \
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" .pushsection .fixup,\"ax\"\n" \
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" .align 2\n" \
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"4: mov %w0, %w6\n" \
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" b 3b\n" \
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" .popsection\n" \
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_ASM_EXTABLE(1b, 4b) \
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_ASM_EXTABLE(2b, 4b) \
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: "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp), \
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"+r" (loops) \
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: "r" (oparg), "Ir" (-EFAULT), "Ir" (-EAGAIN) \
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: "memory"); \
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uaccess_disable(); \
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} while (0)
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static inline int
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arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *_uaddr)
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{
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int oldval = 0, ret, tmp;
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u32 __user *uaddr = __uaccess_mask_ptr(_uaddr);
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pagefault_disable();
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switch (op) {
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case FUTEX_OP_SET:
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__futex_atomic_op("mov %w3, %w5",
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ret, oldval, uaddr, tmp, oparg);
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break;
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case FUTEX_OP_ADD:
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__futex_atomic_op("add %w3, %w1, %w5",
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ret, oldval, uaddr, tmp, oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op("orr %w3, %w1, %w5",
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ret, oldval, uaddr, tmp, oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op("and %w3, %w1, %w5",
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ret, oldval, uaddr, tmp, ~oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op("eor %w3, %w1, %w5",
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ret, oldval, uaddr, tmp, oparg);
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break;
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default:
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ret = -ENOSYS;
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}
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pagefault_enable();
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if (!ret)
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*oval = oldval;
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return ret;
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}
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static inline int
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futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *_uaddr,
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u32 oldval, u32 newval)
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{
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int ret = 0;
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unsigned int loops = FUTEX_MAX_LOOPS;
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u32 val, tmp;
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u32 __user *uaddr;
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if (!access_ok(_uaddr, sizeof(u32)))
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return -EFAULT;
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uaddr = __uaccess_mask_ptr(_uaddr);
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uaccess_enable();
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asm volatile("// futex_atomic_cmpxchg_inatomic\n"
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" prfm pstl1strm, %2\n"
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"1: ldxr %w1, %2\n"
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" sub %w3, %w1, %w5\n"
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" cbnz %w3, 4f\n"
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"2: stlxr %w3, %w6, %2\n"
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" cbz %w3, 3f\n"
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" sub %w4, %w4, %w3\n"
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" cbnz %w4, 1b\n"
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" mov %w0, %w8\n"
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"3:\n"
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" dmb ish\n"
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"4:\n"
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" .pushsection .fixup,\"ax\"\n"
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"5: mov %w0, %w7\n"
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" b 4b\n"
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" .popsection\n"
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_ASM_EXTABLE(1b, 5b)
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_ASM_EXTABLE(2b, 5b)
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: "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp), "+r" (loops)
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: "r" (oldval), "r" (newval), "Ir" (-EFAULT), "Ir" (-EAGAIN)
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: "memory");
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uaccess_disable();
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if (!ret)
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*uval = val;
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return ret;
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}
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#endif /* __KERNEL__ */
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#endif /* __ASM_FUTEX_H */
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