mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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00c8f16236
Most of the kernel assumes that PFN0 is the start of the physical memory (RAM). This assumptions is not true on most of the ARM SOCs and hence and if one try to update the ARM port to follow the assumptions, we end of breaking the dma bounce limit for few block layer drivers. One such example is trying to unify the meaning of max*_pfn on ARM as the bootmem layer expects, breaks few block layer driver dma bounce limit. To fix this problem, we introduce dma_max_pfn(dev) generic helper with a possibility of override from the architecture code. The helper converts a DMA bitmask of bits to a block PFN number. In all the generic cases, it is just "dev->dma_mask >> PAGE_SHIFT" and hence default behavior is maintained as is. Subsequent patches will make use of the helper. No functional change. Cc: Jens Axboe <axboe@kernel.dk> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
271 lines
7.8 KiB
C
271 lines
7.8 KiB
C
#ifndef _LINUX_DMA_MAPPING_H
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#define _LINUX_DMA_MAPPING_H
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#include <linux/string.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/dma-attrs.h>
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#include <linux/dma-direction.h>
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#include <linux/scatterlist.h>
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struct dma_map_ops {
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void* (*alloc)(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp,
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struct dma_attrs *attrs);
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void (*free)(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle,
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struct dma_attrs *attrs);
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int (*mmap)(struct device *, struct vm_area_struct *,
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void *, dma_addr_t, size_t, struct dma_attrs *attrs);
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int (*get_sgtable)(struct device *dev, struct sg_table *sgt, void *,
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dma_addr_t, size_t, struct dma_attrs *attrs);
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dma_addr_t (*map_page)(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction dir,
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struct dma_attrs *attrs);
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void (*unmap_page)(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction dir,
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struct dma_attrs *attrs);
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int (*map_sg)(struct device *dev, struct scatterlist *sg,
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int nents, enum dma_data_direction dir,
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struct dma_attrs *attrs);
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void (*unmap_sg)(struct device *dev,
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struct scatterlist *sg, int nents,
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enum dma_data_direction dir,
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struct dma_attrs *attrs);
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void (*sync_single_for_cpu)(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction dir);
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void (*sync_single_for_device)(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction dir);
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void (*sync_sg_for_cpu)(struct device *dev,
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struct scatterlist *sg, int nents,
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enum dma_data_direction dir);
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void (*sync_sg_for_device)(struct device *dev,
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struct scatterlist *sg, int nents,
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enum dma_data_direction dir);
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int (*mapping_error)(struct device *dev, dma_addr_t dma_addr);
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int (*dma_supported)(struct device *dev, u64 mask);
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int (*set_dma_mask)(struct device *dev, u64 mask);
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#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
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u64 (*get_required_mask)(struct device *dev);
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#endif
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int is_phys;
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};
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#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
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#define DMA_MASK_NONE 0x0ULL
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static inline int valid_dma_direction(int dma_direction)
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{
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return ((dma_direction == DMA_BIDIRECTIONAL) ||
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(dma_direction == DMA_TO_DEVICE) ||
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(dma_direction == DMA_FROM_DEVICE));
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}
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static inline int is_device_dma_capable(struct device *dev)
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{
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return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE;
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}
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#ifdef CONFIG_HAS_DMA
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#include <asm/dma-mapping.h>
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#else
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#include <asm-generic/dma-mapping-broken.h>
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#endif
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static inline u64 dma_get_mask(struct device *dev)
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{
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if (dev && dev->dma_mask && *dev->dma_mask)
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return *dev->dma_mask;
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return DMA_BIT_MASK(32);
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}
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#ifdef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK
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int dma_set_coherent_mask(struct device *dev, u64 mask);
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#else
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static inline int dma_set_coherent_mask(struct device *dev, u64 mask)
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{
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if (!dma_supported(dev, mask))
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return -EIO;
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dev->coherent_dma_mask = mask;
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return 0;
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}
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#endif
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/*
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* Set both the DMA mask and the coherent DMA mask to the same thing.
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* Note that we don't check the return value from dma_set_coherent_mask()
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* as the DMA API guarantees that the coherent DMA mask can be set to
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* the same or smaller than the streaming DMA mask.
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*/
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static inline int dma_set_mask_and_coherent(struct device *dev, u64 mask)
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{
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int rc = dma_set_mask(dev, mask);
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if (rc == 0)
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dma_set_coherent_mask(dev, mask);
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return rc;
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}
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/*
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* Similar to the above, except it deals with the case where the device
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* does not have dev->dma_mask appropriately setup.
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*/
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static inline int dma_coerce_mask_and_coherent(struct device *dev, u64 mask)
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{
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dev->dma_mask = &dev->coherent_dma_mask;
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return dma_set_mask_and_coherent(dev, mask);
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}
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extern u64 dma_get_required_mask(struct device *dev);
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static inline unsigned int dma_get_max_seg_size(struct device *dev)
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{
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return dev->dma_parms ? dev->dma_parms->max_segment_size : 65536;
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}
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static inline unsigned int dma_set_max_seg_size(struct device *dev,
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unsigned int size)
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{
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if (dev->dma_parms) {
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dev->dma_parms->max_segment_size = size;
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return 0;
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} else
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return -EIO;
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}
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static inline unsigned long dma_get_seg_boundary(struct device *dev)
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{
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return dev->dma_parms ?
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dev->dma_parms->segment_boundary_mask : 0xffffffff;
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}
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static inline int dma_set_seg_boundary(struct device *dev, unsigned long mask)
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{
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if (dev->dma_parms) {
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dev->dma_parms->segment_boundary_mask = mask;
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return 0;
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} else
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return -EIO;
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}
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#ifndef dma_max_pfn
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static inline unsigned long dma_max_pfn(struct device *dev)
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{
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return *dev->dma_mask >> PAGE_SHIFT;
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}
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#endif
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static inline void *dma_zalloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag)
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{
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void *ret = dma_alloc_coherent(dev, size, dma_handle,
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flag | __GFP_ZERO);
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return ret;
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}
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#ifdef CONFIG_HAS_DMA
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static inline int dma_get_cache_alignment(void)
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{
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#ifdef ARCH_DMA_MINALIGN
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return ARCH_DMA_MINALIGN;
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#endif
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return 1;
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}
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#endif
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/* flags for the coherent memory api */
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#define DMA_MEMORY_MAP 0x01
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#define DMA_MEMORY_IO 0x02
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#define DMA_MEMORY_INCLUDES_CHILDREN 0x04
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#define DMA_MEMORY_EXCLUSIVE 0x08
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#ifndef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
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static inline int
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dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
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dma_addr_t device_addr, size_t size, int flags)
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{
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return 0;
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}
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static inline void
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dma_release_declared_memory(struct device *dev)
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{
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}
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static inline void *
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dma_mark_declared_memory_occupied(struct device *dev,
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dma_addr_t device_addr, size_t size)
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{
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return ERR_PTR(-EBUSY);
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}
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#endif
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/*
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* Managed DMA API
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*/
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extern void *dmam_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp);
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extern void dmam_free_coherent(struct device *dev, size_t size, void *vaddr,
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dma_addr_t dma_handle);
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extern void *dmam_alloc_noncoherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp);
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extern void dmam_free_noncoherent(struct device *dev, size_t size, void *vaddr,
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dma_addr_t dma_handle);
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#ifdef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
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extern int dmam_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
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dma_addr_t device_addr, size_t size,
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int flags);
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extern void dmam_release_declared_memory(struct device *dev);
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#else /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
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static inline int dmam_declare_coherent_memory(struct device *dev,
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dma_addr_t bus_addr, dma_addr_t device_addr,
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size_t size, gfp_t gfp)
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{
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return 0;
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}
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static inline void dmam_release_declared_memory(struct device *dev)
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{
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}
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#endif /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
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#ifndef CONFIG_HAVE_DMA_ATTRS
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struct dma_attrs;
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#define dma_map_single_attrs(dev, cpu_addr, size, dir, attrs) \
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dma_map_single(dev, cpu_addr, size, dir)
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#define dma_unmap_single_attrs(dev, dma_addr, size, dir, attrs) \
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dma_unmap_single(dev, dma_addr, size, dir)
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#define dma_map_sg_attrs(dev, sgl, nents, dir, attrs) \
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dma_map_sg(dev, sgl, nents, dir)
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#define dma_unmap_sg_attrs(dev, sgl, nents, dir, attrs) \
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dma_unmap_sg(dev, sgl, nents, dir)
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#endif /* CONFIG_HAVE_DMA_ATTRS */
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#ifdef CONFIG_NEED_DMA_MAP_STATE
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#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME
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#define DEFINE_DMA_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME
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#define dma_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME)
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#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL))
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#define dma_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME)
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#define dma_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL))
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#else
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#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME)
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#define DEFINE_DMA_UNMAP_LEN(LEN_NAME)
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#define dma_unmap_addr(PTR, ADDR_NAME) (0)
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#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
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#define dma_unmap_len(PTR, LEN_NAME) (0)
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#define dma_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
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#endif
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#endif
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