Stanimir Varbanov 2a663ed9fe dmaengine: qcom: bam_dma: use correct pipe FIFO size ... The pipe fifo size register must instruct the bam hw how many hw descriptors can be pushed to fifo. Currently we instruct the hw with 32KBytes but wrap the tail in bam_start_dma in BAM_P_EVNT_REG on 4095 i.e. 32760. This leads to stalled transactions when the tail wraps. Fix this by use the correct fifo size in BAM_P_FIFO_SIZES register i.e. 32K - 8. Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>		2016-04-19 21:11:32 +05:30
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bam_dma.c	dmaengine: qcom: bam_dma: use correct pipe FIFO size	2016-04-19 21:11:32 +05:30
hidma_mgmt_sys.c
hidma_mgmt.c
hidma_mgmt.h
hidma.c	dmaengine: add Qualcomm Technologies HIDMA channel driver	2016-03-11 07:42:30 +05:30
hidma.h	dmaengine: add Qualcomm Technologies HIDMA channel driver	2016-03-11 07:42:30 +05:30
Kconfig	dmaengine: add Qualcomm Technologies HIDMA channel driver	2016-03-11 07:42:30 +05:30
Makefile