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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1232d88a47
Presently there are a couple of paths in to the alignment handler, where only the address error path presently quiets the notificiation messages based on the configuration settings. We carry over the notification level tests to the default alignment handler itself incase so that they behave uniformly. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
1019 lines
24 KiB
C
1019 lines
24 KiB
C
/*
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* 'traps.c' handles hardware traps and faults after we have saved some
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* state in 'entry.S'.
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*
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* SuperH version: Copyright (C) 1999 Niibe Yutaka
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* Copyright (C) 2000 Philipp Rumpf
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* Copyright (C) 2000 David Howells
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* Copyright (C) 2002 - 2007 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/ptrace.h>
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#include <linux/hardirq.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/module.h>
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#include <linux/kallsyms.h>
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#include <linux/io.h>
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#include <linux/bug.h>
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#include <linux/debug_locks.h>
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#include <linux/kdebug.h>
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#include <linux/kexec.h>
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#include <linux/limits.h>
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#include <linux/proc_fs.h>
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#include <linux/seq_file.h>
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#include <linux/sysfs.h>
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#include <asm/system.h>
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#include <asm/uaccess.h>
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#include <asm/fpu.h>
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#include <asm/kprobes.h>
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#ifdef CONFIG_CPU_SH2
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# define TRAP_RESERVED_INST 4
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# define TRAP_ILLEGAL_SLOT_INST 6
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# define TRAP_ADDRESS_ERROR 9
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# ifdef CONFIG_CPU_SH2A
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# define TRAP_UBC 12
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# define TRAP_FPU_ERROR 13
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# define TRAP_DIVZERO_ERROR 17
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# define TRAP_DIVOVF_ERROR 18
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# endif
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#else
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#define TRAP_RESERVED_INST 12
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#define TRAP_ILLEGAL_SLOT_INST 13
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#endif
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static unsigned long se_user;
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static unsigned long se_sys;
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static unsigned long se_half;
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static unsigned long se_word;
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static unsigned long se_dword;
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static unsigned long se_multi;
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/* bitfield: 1: warn 2: fixup 4: signal -> combinations 2|4 && 1|2|4 are not
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valid! */
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static int se_usermode = 3;
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/* 0: no warning 1: print a warning message, disabled by default */
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static int se_kernmode_warn;
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#ifdef CONFIG_PROC_FS
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static const char *se_usermode_action[] = {
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"ignored",
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"warn",
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"fixup",
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"fixup+warn",
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"signal",
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"signal+warn"
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};
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static int alignment_proc_show(struct seq_file *m, void *v)
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{
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seq_printf(m, "User:\t\t%lu\n", se_user);
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seq_printf(m, "System:\t\t%lu\n", se_sys);
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seq_printf(m, "Half:\t\t%lu\n", se_half);
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seq_printf(m, "Word:\t\t%lu\n", se_word);
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seq_printf(m, "DWord:\t\t%lu\n", se_dword);
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seq_printf(m, "Multi:\t\t%lu\n", se_multi);
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seq_printf(m, "User faults:\t%i (%s)\n", se_usermode,
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se_usermode_action[se_usermode]);
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seq_printf(m, "Kernel faults:\t%i (fixup%s)\n", se_kernmode_warn,
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se_kernmode_warn ? "+warn" : "");
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return 0;
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}
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static int alignment_proc_open(struct inode *inode, struct file *file)
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{
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return single_open(file, alignment_proc_show, NULL);
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}
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static ssize_t alignment_proc_write(struct file *file,
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const char __user *buffer, size_t count, loff_t *pos)
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{
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int *data = PDE(file->f_path.dentry->d_inode)->data;
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char mode;
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if (count > 0) {
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if (get_user(mode, buffer))
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return -EFAULT;
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if (mode >= '0' && mode <= '5')
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*data = mode - '0';
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}
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return count;
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}
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static const struct file_operations alignment_proc_fops = {
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.owner = THIS_MODULE,
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.open = alignment_proc_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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.write = alignment_proc_write,
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};
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#endif
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static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
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{
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unsigned long p;
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int i;
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printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
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for (p = bottom & ~31; p < top; ) {
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printk("%04lx: ", p & 0xffff);
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for (i = 0; i < 8; i++, p += 4) {
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unsigned int val;
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if (p < bottom || p >= top)
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printk(" ");
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else {
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if (__get_user(val, (unsigned int __user *)p)) {
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printk("\n");
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return;
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}
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printk("%08x ", val);
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}
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}
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printk("\n");
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}
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}
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static DEFINE_SPINLOCK(die_lock);
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void die(const char * str, struct pt_regs * regs, long err)
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{
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static int die_counter;
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oops_enter();
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spin_lock_irq(&die_lock);
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console_verbose();
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bust_spinlocks(1);
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printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
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sysfs_printk_last_file();
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print_modules();
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show_regs(regs);
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printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
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task_pid_nr(current), task_stack_page(current) + 1);
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if (!user_mode(regs) || in_interrupt())
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dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
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(unsigned long)task_stack_page(current));
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notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
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bust_spinlocks(0);
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add_taint(TAINT_DIE);
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spin_unlock_irq(&die_lock);
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oops_exit();
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if (kexec_should_crash(current))
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crash_kexec(regs);
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if (in_interrupt())
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panic("Fatal exception in interrupt");
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if (panic_on_oops)
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panic("Fatal exception");
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do_exit(SIGSEGV);
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}
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static inline void die_if_kernel(const char *str, struct pt_regs *regs,
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long err)
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{
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if (!user_mode(regs))
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die(str, regs, err);
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}
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/*
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* try and fix up kernelspace address errors
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* - userspace errors just cause EFAULT to be returned, resulting in SEGV
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* - kernel/userspace interfaces cause a jump to an appropriate handler
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* - other kernel errors are bad
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*/
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static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
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{
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if (!user_mode(regs)) {
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const struct exception_table_entry *fixup;
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fixup = search_exception_tables(regs->pc);
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if (fixup) {
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regs->pc = fixup->fixup;
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return;
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}
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die(str, regs, err);
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}
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}
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static inline void sign_extend(unsigned int count, unsigned char *dst)
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{
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#ifdef __LITTLE_ENDIAN__
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if ((count == 1) && dst[0] & 0x80) {
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dst[1] = 0xff;
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dst[2] = 0xff;
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dst[3] = 0xff;
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}
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if ((count == 2) && dst[1] & 0x80) {
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dst[2] = 0xff;
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dst[3] = 0xff;
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}
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#else
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if ((count == 1) && dst[3] & 0x80) {
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dst[2] = 0xff;
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dst[1] = 0xff;
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dst[0] = 0xff;
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}
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if ((count == 2) && dst[2] & 0x80) {
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dst[1] = 0xff;
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dst[0] = 0xff;
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}
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#endif
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}
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static struct mem_access user_mem_access = {
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copy_from_user,
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copy_to_user,
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};
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/*
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* handle an instruction that does an unaligned memory access by emulating the
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* desired behaviour
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* - note that PC _may not_ point to the faulting instruction
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* (if that instruction is in a branch delay slot)
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* - return 0 if emulation okay, -EFAULT on existential error
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*/
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static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
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struct mem_access *ma)
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{
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int ret, index, count;
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unsigned long *rm, *rn;
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unsigned char *src, *dst;
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unsigned char __user *srcu, *dstu;
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index = (instruction>>8)&15; /* 0x0F00 */
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rn = ®s->regs[index];
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index = (instruction>>4)&15; /* 0x00F0 */
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rm = ®s->regs[index];
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count = 1<<(instruction&3);
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switch (count) {
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case 1: se_half += 1; break;
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case 2: se_word += 1; break;
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case 4: se_dword += 1; break;
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case 8: se_multi += 1; break; /* ??? */
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}
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ret = -EFAULT;
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switch (instruction>>12) {
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case 0: /* mov.[bwl] to/from memory via r0+rn */
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if (instruction & 8) {
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/* from memory */
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srcu = (unsigned char __user *)*rm;
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srcu += regs->regs[0];
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dst = (unsigned char *)rn;
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*(unsigned long *)dst = 0;
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#if !defined(__LITTLE_ENDIAN__)
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dst += 4-count;
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#endif
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if (ma->from(dst, srcu, count))
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goto fetch_fault;
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sign_extend(count, dst);
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} else {
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/* to memory */
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src = (unsigned char *)rm;
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#if !defined(__LITTLE_ENDIAN__)
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src += 4-count;
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#endif
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dstu = (unsigned char __user *)*rn;
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dstu += regs->regs[0];
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if (ma->to(dstu, src, count))
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goto fetch_fault;
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}
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ret = 0;
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break;
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case 1: /* mov.l Rm,@(disp,Rn) */
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src = (unsigned char*) rm;
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dstu = (unsigned char __user *)*rn;
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dstu += (instruction&0x000F)<<2;
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if (ma->to(dstu, src, 4))
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goto fetch_fault;
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ret = 0;
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break;
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case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
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if (instruction & 4)
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*rn -= count;
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src = (unsigned char*) rm;
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dstu = (unsigned char __user *)*rn;
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#if !defined(__LITTLE_ENDIAN__)
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src += 4-count;
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#endif
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if (ma->to(dstu, src, count))
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goto fetch_fault;
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ret = 0;
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break;
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case 5: /* mov.l @(disp,Rm),Rn */
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srcu = (unsigned char __user *)*rm;
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srcu += (instruction & 0x000F) << 2;
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dst = (unsigned char *)rn;
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*(unsigned long *)dst = 0;
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if (ma->from(dst, srcu, 4))
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goto fetch_fault;
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ret = 0;
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break;
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case 6: /* mov.[bwl] from memory, possibly with post-increment */
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srcu = (unsigned char __user *)*rm;
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if (instruction & 4)
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*rm += count;
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dst = (unsigned char*) rn;
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*(unsigned long*)dst = 0;
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#if !defined(__LITTLE_ENDIAN__)
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dst += 4-count;
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#endif
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if (ma->from(dst, srcu, count))
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goto fetch_fault;
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sign_extend(count, dst);
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ret = 0;
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break;
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case 8:
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switch ((instruction&0xFF00)>>8) {
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case 0x81: /* mov.w R0,@(disp,Rn) */
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src = (unsigned char *) ®s->regs[0];
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#if !defined(__LITTLE_ENDIAN__)
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src += 2;
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#endif
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dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
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dstu += (instruction & 0x000F) << 1;
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if (ma->to(dstu, src, 2))
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goto fetch_fault;
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ret = 0;
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break;
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case 0x85: /* mov.w @(disp,Rm),R0 */
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srcu = (unsigned char __user *)*rm;
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srcu += (instruction & 0x000F) << 1;
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dst = (unsigned char *) ®s->regs[0];
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*(unsigned long *)dst = 0;
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#if !defined(__LITTLE_ENDIAN__)
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dst += 2;
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#endif
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if (ma->from(dst, srcu, 2))
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goto fetch_fault;
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sign_extend(2, dst);
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ret = 0;
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break;
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}
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break;
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}
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return ret;
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fetch_fault:
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/* Argh. Address not only misaligned but also non-existent.
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* Raise an EFAULT and see if it's trapped
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*/
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die_if_no_fixup("Fault in unaligned fixup", regs, 0);
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return -EFAULT;
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}
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/*
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* emulate the instruction in the delay slot
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* - fetches the instruction from PC+2
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*/
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static inline int handle_delayslot(struct pt_regs *regs,
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insn_size_t old_instruction,
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struct mem_access *ma)
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{
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insn_size_t instruction;
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void __user *addr = (void __user *)(regs->pc +
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instruction_size(old_instruction));
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|
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if (copy_from_user(&instruction, addr, sizeof(instruction))) {
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/* the instruction-fetch faulted */
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if (user_mode(regs))
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return -EFAULT;
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|
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/* kernel */
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die("delay-slot-insn faulting in handle_unaligned_delayslot",
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regs, 0);
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}
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return handle_unaligned_ins(instruction, regs, ma);
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}
|
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|
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/*
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* handle an instruction that does an unaligned memory access
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* - have to be careful of branch delay-slot instructions that fault
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* SH3:
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* - if the branch would be taken PC points to the branch
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* - if the branch would not be taken, PC points to delay-slot
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* SH4:
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* - PC always points to delayed branch
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* - return 0 if handled, -EFAULT if failed (may not return if in kernel)
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*/
|
|
|
|
/* Macros to determine offset from current PC for branch instructions */
|
|
/* Explicit type coercion is used to force sign extension where needed */
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#define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
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#define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
|
|
|
|
int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
|
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struct mem_access *ma, int expected)
|
|
{
|
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u_int rm;
|
|
int ret, index;
|
|
|
|
/*
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|
* XXX: We can't handle mixed 16/32-bit instructions yet
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|
*/
|
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if (instruction_size(instruction) != 2)
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return -EINVAL;
|
|
|
|
index = (instruction>>8)&15; /* 0x0F00 */
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rm = regs->regs[index];
|
|
|
|
/* shout about fixups */
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|
if (!expected) {
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if (user_mode(regs) && (se_usermode & 1) && printk_ratelimit())
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|
pr_notice("Fixing up unaligned userspace access "
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|
"in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
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current->comm, task_pid_nr(current),
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(void *)regs->pc, instruction);
|
|
else if (se_kernmode_warn && printk_ratelimit())
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|
pr_notice("Fixing up unaligned kernel access "
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|
"in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
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|
current->comm, task_pid_nr(current),
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|
(void *)regs->pc, instruction);
|
|
}
|
|
|
|
ret = -EFAULT;
|
|
switch (instruction&0xF000) {
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|
case 0x0000:
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if (instruction==0x000B) {
|
|
/* rts */
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|
ret = handle_delayslot(regs, instruction, ma);
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|
if (ret==0)
|
|
regs->pc = regs->pr;
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|
}
|
|
else if ((instruction&0x00FF)==0x0023) {
|
|
/* braf @Rm */
|
|
ret = handle_delayslot(regs, instruction, ma);
|
|
if (ret==0)
|
|
regs->pc += rm + 4;
|
|
}
|
|
else if ((instruction&0x00FF)==0x0003) {
|
|
/* bsrf @Rm */
|
|
ret = handle_delayslot(regs, instruction, ma);
|
|
if (ret==0) {
|
|
regs->pr = regs->pc + 4;
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regs->pc += rm + 4;
|
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}
|
|
}
|
|
else {
|
|
/* mov.[bwl] to/from memory via r0+rn */
|
|
goto simple;
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|
}
|
|
break;
|
|
|
|
case 0x1000: /* mov.l Rm,@(disp,Rn) */
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|
goto simple;
|
|
|
|
case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
|
|
goto simple;
|
|
|
|
case 0x4000:
|
|
if ((instruction&0x00FF)==0x002B) {
|
|
/* jmp @Rm */
|
|
ret = handle_delayslot(regs, instruction, ma);
|
|
if (ret==0)
|
|
regs->pc = rm;
|
|
}
|
|
else if ((instruction&0x00FF)==0x000B) {
|
|
/* jsr @Rm */
|
|
ret = handle_delayslot(regs, instruction, ma);
|
|
if (ret==0) {
|
|
regs->pr = regs->pc + 4;
|
|
regs->pc = rm;
|
|
}
|
|
}
|
|
else {
|
|
/* mov.[bwl] to/from memory via r0+rn */
|
|
goto simple;
|
|
}
|
|
break;
|
|
|
|
case 0x5000: /* mov.l @(disp,Rm),Rn */
|
|
goto simple;
|
|
|
|
case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
|
|
goto simple;
|
|
|
|
case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
|
|
switch (instruction&0x0F00) {
|
|
case 0x0100: /* mov.w R0,@(disp,Rm) */
|
|
goto simple;
|
|
case 0x0500: /* mov.w @(disp,Rm),R0 */
|
|
goto simple;
|
|
case 0x0B00: /* bf lab - no delayslot*/
|
|
break;
|
|
case 0x0F00: /* bf/s lab */
|
|
ret = handle_delayslot(regs, instruction, ma);
|
|
if (ret==0) {
|
|
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
|
|
if ((regs->sr & 0x00000001) != 0)
|
|
regs->pc += 4; /* next after slot */
|
|
else
|
|
#endif
|
|
regs->pc += SH_PC_8BIT_OFFSET(instruction);
|
|
}
|
|
break;
|
|
case 0x0900: /* bt lab - no delayslot */
|
|
break;
|
|
case 0x0D00: /* bt/s lab */
|
|
ret = handle_delayslot(regs, instruction, ma);
|
|
if (ret==0) {
|
|
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
|
|
if ((regs->sr & 0x00000001) == 0)
|
|
regs->pc += 4; /* next after slot */
|
|
else
|
|
#endif
|
|
regs->pc += SH_PC_8BIT_OFFSET(instruction);
|
|
}
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case 0xA000: /* bra label */
|
|
ret = handle_delayslot(regs, instruction, ma);
|
|
if (ret==0)
|
|
regs->pc += SH_PC_12BIT_OFFSET(instruction);
|
|
break;
|
|
|
|
case 0xB000: /* bsr label */
|
|
ret = handle_delayslot(regs, instruction, ma);
|
|
if (ret==0) {
|
|
regs->pr = regs->pc + 4;
|
|
regs->pc += SH_PC_12BIT_OFFSET(instruction);
|
|
}
|
|
break;
|
|
}
|
|
return ret;
|
|
|
|
/* handle non-delay-slot instruction */
|
|
simple:
|
|
ret = handle_unaligned_ins(instruction, regs, ma);
|
|
if (ret==0)
|
|
regs->pc += instruction_size(instruction);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Handle various address error exceptions:
|
|
* - instruction address error:
|
|
* misaligned PC
|
|
* PC >= 0x80000000 in user mode
|
|
* - data address error (read and write)
|
|
* misaligned data access
|
|
* access to >= 0x80000000 is user mode
|
|
* Unfortuntaly we can't distinguish between instruction address error
|
|
* and data address errors caused by read accesses.
|
|
*/
|
|
asmlinkage void do_address_error(struct pt_regs *regs,
|
|
unsigned long writeaccess,
|
|
unsigned long address)
|
|
{
|
|
unsigned long error_code = 0;
|
|
mm_segment_t oldfs;
|
|
siginfo_t info;
|
|
insn_size_t instruction;
|
|
int tmp;
|
|
|
|
/* Intentional ifdef */
|
|
#ifdef CONFIG_CPU_HAS_SR_RB
|
|
error_code = lookup_exception_vector();
|
|
#endif
|
|
|
|
oldfs = get_fs();
|
|
|
|
if (user_mode(regs)) {
|
|
int si_code = BUS_ADRERR;
|
|
|
|
local_irq_enable();
|
|
|
|
se_user += 1;
|
|
|
|
set_fs(USER_DS);
|
|
if (copy_from_user(&instruction, (insn_size_t *)(regs->pc & ~1),
|
|
sizeof(instruction))) {
|
|
set_fs(oldfs);
|
|
goto uspace_segv;
|
|
}
|
|
set_fs(oldfs);
|
|
|
|
/* shout about userspace fixups */
|
|
if (se_usermode & 1)
|
|
printk(KERN_NOTICE "Unaligned userspace access "
|
|
"in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
|
|
current->comm, current->pid, (void *)regs->pc,
|
|
instruction);
|
|
|
|
if (se_usermode & 2)
|
|
goto fixup;
|
|
|
|
if (se_usermode & 4)
|
|
goto uspace_segv;
|
|
else {
|
|
/* ignore */
|
|
regs->pc += instruction_size(instruction);
|
|
return;
|
|
}
|
|
|
|
fixup:
|
|
/* bad PC is not something we can fix */
|
|
if (regs->pc & 1) {
|
|
si_code = BUS_ADRALN;
|
|
goto uspace_segv;
|
|
}
|
|
|
|
set_fs(USER_DS);
|
|
tmp = handle_unaligned_access(instruction, regs,
|
|
&user_mem_access, 0);
|
|
set_fs(oldfs);
|
|
|
|
if (tmp==0)
|
|
return; /* sorted */
|
|
uspace_segv:
|
|
printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
|
|
"access (PC %lx PR %lx)\n", current->comm, regs->pc,
|
|
regs->pr);
|
|
|
|
info.si_signo = SIGBUS;
|
|
info.si_errno = 0;
|
|
info.si_code = si_code;
|
|
info.si_addr = (void __user *)address;
|
|
force_sig_info(SIGBUS, &info, current);
|
|
} else {
|
|
se_sys += 1;
|
|
|
|
if (regs->pc & 1)
|
|
die("unaligned program counter", regs, error_code);
|
|
|
|
set_fs(KERNEL_DS);
|
|
if (copy_from_user(&instruction, (void __user *)(regs->pc),
|
|
sizeof(instruction))) {
|
|
/* Argh. Fault on the instruction itself.
|
|
This should never happen non-SMP
|
|
*/
|
|
set_fs(oldfs);
|
|
die("insn faulting in do_address_error", regs, 0);
|
|
}
|
|
|
|
if (se_kernmode_warn)
|
|
printk(KERN_NOTICE "Unaligned kernel access "
|
|
"on behalf of \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
|
|
current->comm, current->pid, (void *)regs->pc,
|
|
instruction);
|
|
|
|
handle_unaligned_access(instruction, regs,
|
|
&user_mem_access, 0);
|
|
set_fs(oldfs);
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_SH_DSP
|
|
/*
|
|
* SH-DSP support gerg@snapgear.com.
|
|
*/
|
|
int is_dsp_inst(struct pt_regs *regs)
|
|
{
|
|
unsigned short inst = 0;
|
|
|
|
/*
|
|
* Safe guard if DSP mode is already enabled or we're lacking
|
|
* the DSP altogether.
|
|
*/
|
|
if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
|
|
return 0;
|
|
|
|
get_user(inst, ((unsigned short *) regs->pc));
|
|
|
|
inst &= 0xf000;
|
|
|
|
/* Check for any type of DSP or support instruction */
|
|
if ((inst == 0xf000) || (inst == 0x4000))
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
#define is_dsp_inst(regs) (0)
|
|
#endif /* CONFIG_SH_DSP */
|
|
|
|
#ifdef CONFIG_CPU_SH2A
|
|
asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
|
|
unsigned long r6, unsigned long r7,
|
|
struct pt_regs __regs)
|
|
{
|
|
siginfo_t info;
|
|
|
|
switch (r4) {
|
|
case TRAP_DIVZERO_ERROR:
|
|
info.si_code = FPE_INTDIV;
|
|
break;
|
|
case TRAP_DIVOVF_ERROR:
|
|
info.si_code = FPE_INTOVF;
|
|
break;
|
|
}
|
|
|
|
force_sig_info(SIGFPE, &info, current);
|
|
}
|
|
#endif
|
|
|
|
asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
|
|
unsigned long r6, unsigned long r7,
|
|
struct pt_regs __regs)
|
|
{
|
|
struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
|
|
unsigned long error_code;
|
|
struct task_struct *tsk = current;
|
|
|
|
#ifdef CONFIG_SH_FPU_EMU
|
|
unsigned short inst = 0;
|
|
int err;
|
|
|
|
get_user(inst, (unsigned short*)regs->pc);
|
|
|
|
err = do_fpu_inst(inst, regs);
|
|
if (!err) {
|
|
regs->pc += instruction_size(inst);
|
|
return;
|
|
}
|
|
/* not a FPU inst. */
|
|
#endif
|
|
|
|
#ifdef CONFIG_SH_DSP
|
|
/* Check if it's a DSP instruction */
|
|
if (is_dsp_inst(regs)) {
|
|
/* Enable DSP mode, and restart instruction. */
|
|
regs->sr |= SR_DSP;
|
|
/* Save DSP mode */
|
|
tsk->thread.dsp_status.status |= SR_DSP;
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
error_code = lookup_exception_vector();
|
|
|
|
local_irq_enable();
|
|
force_sig(SIGILL, tsk);
|
|
die_if_no_fixup("reserved instruction", regs, error_code);
|
|
}
|
|
|
|
#ifdef CONFIG_SH_FPU_EMU
|
|
static int emulate_branch(unsigned short inst, struct pt_regs *regs)
|
|
{
|
|
/*
|
|
* bfs: 8fxx: PC+=d*2+4;
|
|
* bts: 8dxx: PC+=d*2+4;
|
|
* bra: axxx: PC+=D*2+4;
|
|
* bsr: bxxx: PC+=D*2+4 after PR=PC+4;
|
|
* braf:0x23: PC+=Rn*2+4;
|
|
* bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
|
|
* jmp: 4x2b: PC=Rn;
|
|
* jsr: 4x0b: PC=Rn after PR=PC+4;
|
|
* rts: 000b: PC=PR;
|
|
*/
|
|
if (((inst & 0xf000) == 0xb000) || /* bsr */
|
|
((inst & 0xf0ff) == 0x0003) || /* bsrf */
|
|
((inst & 0xf0ff) == 0x400b)) /* jsr */
|
|
regs->pr = regs->pc + 4;
|
|
|
|
if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */
|
|
regs->pc += SH_PC_8BIT_OFFSET(inst);
|
|
return 0;
|
|
}
|
|
|
|
if ((inst & 0xe000) == 0xa000) { /* bra, bsr */
|
|
regs->pc += SH_PC_12BIT_OFFSET(inst);
|
|
return 0;
|
|
}
|
|
|
|
if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */
|
|
regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
|
|
return 0;
|
|
}
|
|
|
|
if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */
|
|
regs->pc = regs->regs[(inst & 0x0f00) >> 8];
|
|
return 0;
|
|
}
|
|
|
|
if ((inst & 0xffff) == 0x000b) { /* rts */
|
|
regs->pc = regs->pr;
|
|
return 0;
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
#endif
|
|
|
|
asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
|
|
unsigned long r6, unsigned long r7,
|
|
struct pt_regs __regs)
|
|
{
|
|
struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
|
|
unsigned long inst;
|
|
struct task_struct *tsk = current;
|
|
|
|
if (kprobe_handle_illslot(regs->pc) == 0)
|
|
return;
|
|
|
|
#ifdef CONFIG_SH_FPU_EMU
|
|
get_user(inst, (unsigned short *)regs->pc + 1);
|
|
if (!do_fpu_inst(inst, regs)) {
|
|
get_user(inst, (unsigned short *)regs->pc);
|
|
if (!emulate_branch(inst, regs))
|
|
return;
|
|
/* fault in branch.*/
|
|
}
|
|
/* not a FPU inst. */
|
|
#endif
|
|
|
|
inst = lookup_exception_vector();
|
|
|
|
local_irq_enable();
|
|
force_sig(SIGILL, tsk);
|
|
die_if_no_fixup("illegal slot instruction", regs, inst);
|
|
}
|
|
|
|
asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
|
|
unsigned long r6, unsigned long r7,
|
|
struct pt_regs __regs)
|
|
{
|
|
struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
|
|
long ex;
|
|
|
|
ex = lookup_exception_vector();
|
|
die_if_kernel("exception", regs, ex);
|
|
}
|
|
|
|
#if defined(CONFIG_SH_STANDARD_BIOS)
|
|
void *gdb_vbr_vector;
|
|
|
|
static inline void __init gdb_vbr_init(void)
|
|
{
|
|
register unsigned long vbr;
|
|
|
|
/*
|
|
* Read the old value of the VBR register to initialise
|
|
* the vector through which debug and BIOS traps are
|
|
* delegated by the Linux trap handler.
|
|
*/
|
|
asm volatile("stc vbr, %0" : "=r" (vbr));
|
|
|
|
gdb_vbr_vector = (void *)(vbr + 0x100);
|
|
printk("Setting GDB trap vector to 0x%08lx\n",
|
|
(unsigned long)gdb_vbr_vector);
|
|
}
|
|
#endif
|
|
|
|
void __cpuinit per_cpu_trap_init(void)
|
|
{
|
|
extern void *vbr_base;
|
|
|
|
#ifdef CONFIG_SH_STANDARD_BIOS
|
|
if (raw_smp_processor_id() == 0)
|
|
gdb_vbr_init();
|
|
#endif
|
|
|
|
/* NOTE: The VBR value should be at P1
|
|
(or P2, virtural "fixed" address space).
|
|
It's definitely should not in physical address. */
|
|
|
|
asm volatile("ldc %0, vbr"
|
|
: /* no output */
|
|
: "r" (&vbr_base)
|
|
: "memory");
|
|
}
|
|
|
|
void *set_exception_table_vec(unsigned int vec, void *handler)
|
|
{
|
|
extern void *exception_handling_table[];
|
|
void *old_handler;
|
|
|
|
old_handler = exception_handling_table[vec];
|
|
exception_handling_table[vec] = handler;
|
|
return old_handler;
|
|
}
|
|
|
|
void __init trap_init(void)
|
|
{
|
|
set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
|
|
set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
|
|
|
|
#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
|
|
defined(CONFIG_SH_FPU_EMU)
|
|
/*
|
|
* For SH-4 lacking an FPU, treat floating point instructions as
|
|
* reserved. They'll be handled in the math-emu case, or faulted on
|
|
* otherwise.
|
|
*/
|
|
set_exception_table_evt(0x800, do_reserved_inst);
|
|
set_exception_table_evt(0x820, do_illegal_slot_inst);
|
|
#elif defined(CONFIG_SH_FPU)
|
|
set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
|
|
set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
|
|
#endif
|
|
|
|
#ifdef CONFIG_CPU_SH2
|
|
set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
|
|
#endif
|
|
#ifdef CONFIG_CPU_SH2A
|
|
set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
|
|
set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
|
|
#ifdef CONFIG_SH_FPU
|
|
set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef TRAP_UBC
|
|
set_exception_table_vec(TRAP_UBC, break_point_trap);
|
|
#endif
|
|
|
|
/* Setup VBR for boot cpu */
|
|
per_cpu_trap_init();
|
|
}
|
|
|
|
void show_stack(struct task_struct *tsk, unsigned long *sp)
|
|
{
|
|
unsigned long stack;
|
|
|
|
if (!tsk)
|
|
tsk = current;
|
|
if (tsk == current)
|
|
sp = (unsigned long *)current_stack_pointer;
|
|
else
|
|
sp = (unsigned long *)tsk->thread.sp;
|
|
|
|
stack = (unsigned long)sp;
|
|
dump_mem("Stack: ", stack, THREAD_SIZE +
|
|
(unsigned long)task_stack_page(tsk));
|
|
show_trace(tsk, sp, NULL);
|
|
}
|
|
|
|
void dump_stack(void)
|
|
{
|
|
show_stack(NULL, NULL);
|
|
}
|
|
EXPORT_SYMBOL(dump_stack);
|
|
|
|
#ifdef CONFIG_PROC_FS
|
|
/*
|
|
* This needs to be done after sysctl_init, otherwise sys/ will be
|
|
* overwritten. Actually, this shouldn't be in sys/ at all since
|
|
* it isn't a sysctl, and it doesn't contain sysctl information.
|
|
* We now locate it in /proc/cpu/alignment instead.
|
|
*/
|
|
static int __init alignment_init(void)
|
|
{
|
|
struct proc_dir_entry *dir, *res;
|
|
|
|
dir = proc_mkdir("cpu", NULL);
|
|
if (!dir)
|
|
return -ENOMEM;
|
|
|
|
res = proc_create_data("alignment", S_IWUSR | S_IRUGO, dir,
|
|
&alignment_proc_fops, &se_usermode);
|
|
if (!res)
|
|
return -ENOMEM;
|
|
|
|
res = proc_create_data("kernel_alignment", S_IWUSR | S_IRUGO, dir,
|
|
&alignment_proc_fops, &se_kernmode_warn);
|
|
if (!res)
|
|
return -ENOMEM;
|
|
|
|
return 0;
|
|
}
|
|
|
|
fs_initcall(alignment_init);
|
|
#endif
|