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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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d4f513ff12
sys_clk has multiple parents and selection of parent depends on sys_clk_ctrl register bit no. 23:25, with following possibilities 0XX: pll1_clk 10X: sys_synth_clk 110: pll2_clk 111: pll3_clk Out of several possibilities (h/w wise) to select same clock parent for sys_clk, current clock implementation was considering just one value. When bootloader programmed different (valid) value to select a clock parent then Linux breaks. Here, we try to include all possibilities which can lead to same clock selection thus making Linux independent of bootloader selection values. Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> |
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| .. | ||
| clk-aux-synth.c | ||
| clk-frac-synth.c | ||
| clk-gpt-synth.c | ||
| clk-vco-pll.c | ||
| clk.c | ||
| clk.h | ||
| Makefile | ||
| spear3xx_clock.c | ||
| spear6xx_clock.c | ||
| spear1310_clock.c | ||
| spear1340_clock.c | ||