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29dfc6bbcc
The Allwinner H6 SoC have its pin controllers with the first IRQ-capable GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. Some refactors in the sunxi pinctrl framework are needed. This commit introduces a IRQ bank conversion function, which replaces the "(bank_base + bank)" code in IRQ register access. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
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.. | ||
Kconfig | ||
Makefile | ||
pinctrl-sun4i-a10.c | ||
pinctrl-sun5i.c | ||
pinctrl-sun6i-a31-r.c | ||
pinctrl-sun6i-a31.c | ||
pinctrl-sun8i-a23-r.c | ||
pinctrl-sun8i-a23.c | ||
pinctrl-sun8i-a33.c | ||
pinctrl-sun8i-a83t-r.c | ||
pinctrl-sun8i-a83t.c | ||
pinctrl-sun8i-h3-r.c | ||
pinctrl-sun8i-h3.c | ||
pinctrl-sun8i-v3s.c | ||
pinctrl-sun9i-a80-r.c | ||
pinctrl-sun9i-a80.c | ||
pinctrl-sun50i-a64-r.c | ||
pinctrl-sun50i-a64.c | ||
pinctrl-sun50i-h5.c | ||
pinctrl-sunxi.c | ||
pinctrl-sunxi.h |