mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
b5f8ffbb6f
Convert DRA7xx to use the new clockdomain based layout. Previously the clkctrl split was based on CM isntance boundaries. The new layout helps with introducing the interconnect driver instances. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
84 lines
2.2 KiB
Plaintext
84 lines
2.2 KiB
Plaintext
/*
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* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "dra74x.dtsi"
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/ {
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compatible = "ti,dra762", "ti,dra7";
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ocp {
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target-module@42c01900 {
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compatible = "ti,sysc-dra7-mcan", "ti,sysc";
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ranges = <0x0 0x42c00000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x42c01900 0x4>,
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<0x42c01904 0x4>,
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<0x42c01908 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET |
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SYSC_DRA7_MCAN_ENAWAKEUP)>;
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ti,syss-mask = <1>;
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clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>;
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clock-names = "fck";
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m_can0: mcan@1a00 {
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compatible = "bosch,m_can";
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reg = <0x1a00 0x4000>, <0x0 0x18FC>;
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reg-names = "m_can", "message_ram";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&mcan_clk>, <&l3_iclk_div>;
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clock-names = "cclk", "hclk";
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bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
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};
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};
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};
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};
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/* MCAN interrupts are hard-wired to irqs 67, 68 */
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&crossbar_mpu {
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ti,irqs-skip = <10 67 68 133 139 140>;
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};
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&scm_conf_clocks {
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dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_gmac_x2_ck>;
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ti,max-div = <63>;
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reg = <0x03fc>;
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ti,bit-shift=<20>;
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ti,latch-bit=<26>;
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assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>;
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assigned-clock-rates = <80000000>;
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};
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dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>;
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reg = <0x3fc>;
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ti,bit-shift = <29>;
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ti,latch-bit=<26>;
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assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
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assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>;
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};
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mcan_clk: mcan_clk@3fc {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
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ti,bit-shift = <27>;
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reg = <0x3fc>;
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};
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};
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