mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 12:36:45 +07:00
84a5ead18e
This patch add support for the Mediatek MT2701 DISP subsystem. There is only one OVL engine in MT2701. Signed-off-by: YT Shen <yt.shen@mediatek.com> Acked-by: CK Hu <ck.hu@mediatek.com>
424 lines
12 KiB
C
424 lines
12 KiB
C
/*
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* Copyright (c) 2015 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "mtk_drm_ddp.h"
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#include "mtk_drm_ddp_comp.h"
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#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
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#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
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#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
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#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
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#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
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#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
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#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
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#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
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#define DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN 0x0c8
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#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
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#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
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#define DISP_REG_CONFIG_OUT_SEL 0x04c
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#define DISP_REG_CONFIG_DSI_SEL 0x050
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#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
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#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
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#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
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#define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
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#define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
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#define INT_MUTEX BIT(1)
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#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
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#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
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#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
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#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
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#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
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#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
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#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
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#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
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#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
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#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
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#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
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#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
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#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
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#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
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#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
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#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
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#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
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#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
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#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
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#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
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#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
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#define MUTEX_SOF_SINGLE_MODE 0
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#define MUTEX_SOF_DSI0 1
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#define MUTEX_SOF_DSI1 2
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#define MUTEX_SOF_DPI0 3
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#define OVL0_MOUT_EN_COLOR0 0x1
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#define OD_MOUT_EN_RDMA0 0x1
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#define UFOE_MOUT_EN_DSI0 0x1
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#define COLOR0_SEL_IN_OVL0 0x1
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#define OVL1_MOUT_EN_COLOR1 0x1
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#define GAMMA_MOUT_EN_RDMA1 0x1
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#define RDMA1_MOUT_DPI0 0x2
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#define DPI0_SEL_IN_RDMA1 0x1
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#define COLOR1_SEL_IN_OVL1 0x1
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#define OVL_MOUT_EN_RDMA 0x1
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#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
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#define DSI_SEL_IN_BLS 0x0
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struct mtk_disp_mutex {
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int id;
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bool claimed;
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};
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struct mtk_ddp {
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struct device *dev;
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struct clk *clk;
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void __iomem *regs;
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struct mtk_disp_mutex mutex[10];
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const unsigned int *mutex_mod;
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};
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static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
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[DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
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[DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
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[DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
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[DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0,
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[DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1,
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[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
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};
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static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
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[DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL,
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[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
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[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
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[DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA,
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[DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD,
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[DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0,
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[DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1,
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[DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0,
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[DDP_COMPONENT_PWM1] = MT8173_MUTEX_MOD_DISP_PWM1,
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[DDP_COMPONENT_RDMA0] = MT8173_MUTEX_MOD_DISP_RDMA0,
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[DDP_COMPONENT_RDMA1] = MT8173_MUTEX_MOD_DISP_RDMA1,
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[DDP_COMPONENT_RDMA2] = MT8173_MUTEX_MOD_DISP_RDMA2,
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[DDP_COMPONENT_UFOE] = MT8173_MUTEX_MOD_DISP_UFOE,
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[DDP_COMPONENT_WDMA0] = MT8173_MUTEX_MOD_DISP_WDMA0,
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[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
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};
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static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
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enum mtk_ddp_comp_id next,
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unsigned int *addr)
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{
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unsigned int value;
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if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
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*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
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value = OVL0_MOUT_EN_COLOR0;
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} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
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*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
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value = OVL_MOUT_EN_RDMA;
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} else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) {
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*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
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value = OD_MOUT_EN_RDMA0;
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} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
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*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
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value = UFOE_MOUT_EN_DSI0;
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} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
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*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
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value = OVL1_MOUT_EN_COLOR1;
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} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
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*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
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value = GAMMA_MOUT_EN_RDMA1;
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} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
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*addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN;
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value = RDMA1_MOUT_DPI0;
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} else {
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value = 0;
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}
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return value;
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}
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static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
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enum mtk_ddp_comp_id next,
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unsigned int *addr)
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{
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unsigned int value;
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if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
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*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
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value = COLOR0_SEL_IN_OVL0;
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} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
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*addr = DISP_REG_CONFIG_DPI_SEL_IN;
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value = DPI0_SEL_IN_RDMA1;
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} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
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*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
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value = COLOR1_SEL_IN_OVL1;
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} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
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*addr = DISP_REG_CONFIG_DSI_SEL;
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value = DSI_SEL_IN_BLS;
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} else {
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value = 0;
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}
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return value;
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}
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static void mtk_ddp_sout_sel(void __iomem *config_regs,
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enum mtk_ddp_comp_id cur,
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enum mtk_ddp_comp_id next)
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{
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if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0)
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writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
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config_regs + DISP_REG_CONFIG_OUT_SEL);
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}
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void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
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enum mtk_ddp_comp_id cur,
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enum mtk_ddp_comp_id next)
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{
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unsigned int addr, value, reg;
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value = mtk_ddp_mout_en(cur, next, &addr);
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if (value) {
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reg = readl_relaxed(config_regs + addr) | value;
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writel_relaxed(reg, config_regs + addr);
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}
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mtk_ddp_sout_sel(config_regs, cur, next);
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value = mtk_ddp_sel_in(cur, next, &addr);
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if (value) {
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reg = readl_relaxed(config_regs + addr) | value;
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writel_relaxed(reg, config_regs + addr);
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}
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}
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void mtk_ddp_remove_comp_from_path(void __iomem *config_regs,
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enum mtk_ddp_comp_id cur,
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enum mtk_ddp_comp_id next)
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{
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unsigned int addr, value, reg;
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value = mtk_ddp_mout_en(cur, next, &addr);
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if (value) {
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reg = readl_relaxed(config_regs + addr) & ~value;
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writel_relaxed(reg, config_regs + addr);
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}
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value = mtk_ddp_sel_in(cur, next, &addr);
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if (value) {
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reg = readl_relaxed(config_regs + addr) & ~value;
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writel_relaxed(reg, config_regs + addr);
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}
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}
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struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id)
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{
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struct mtk_ddp *ddp = dev_get_drvdata(dev);
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if (id >= 10)
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return ERR_PTR(-EINVAL);
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if (ddp->mutex[id].claimed)
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return ERR_PTR(-EBUSY);
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ddp->mutex[id].claimed = true;
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return &ddp->mutex[id];
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}
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void mtk_disp_mutex_put(struct mtk_disp_mutex *mutex)
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{
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struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
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mutex[mutex->id]);
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WARN_ON(&ddp->mutex[mutex->id] != mutex);
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mutex->claimed = false;
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}
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int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex)
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{
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struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
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mutex[mutex->id]);
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return clk_prepare_enable(ddp->clk);
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}
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void mtk_disp_mutex_unprepare(struct mtk_disp_mutex *mutex)
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{
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struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
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mutex[mutex->id]);
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clk_disable_unprepare(ddp->clk);
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}
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void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
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enum mtk_ddp_comp_id id)
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{
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struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
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mutex[mutex->id]);
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unsigned int reg;
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WARN_ON(&ddp->mutex[mutex->id] != mutex);
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switch (id) {
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case DDP_COMPONENT_DSI0:
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reg = MUTEX_SOF_DSI0;
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break;
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case DDP_COMPONENT_DSI1:
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reg = MUTEX_SOF_DSI0;
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break;
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case DDP_COMPONENT_DPI0:
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reg = MUTEX_SOF_DPI0;
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break;
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default:
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reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
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reg |= ddp->mutex_mod[id];
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writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
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return;
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}
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writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_SOF(mutex->id));
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}
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void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex,
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enum mtk_ddp_comp_id id)
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{
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struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
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mutex[mutex->id]);
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unsigned int reg;
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WARN_ON(&ddp->mutex[mutex->id] != mutex);
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switch (id) {
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case DDP_COMPONENT_DSI0:
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case DDP_COMPONENT_DSI1:
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case DDP_COMPONENT_DPI0:
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writel_relaxed(MUTEX_SOF_SINGLE_MODE,
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ddp->regs + DISP_REG_MUTEX_SOF(mutex->id));
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break;
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default:
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reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
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reg &= ~(ddp->mutex_mod[id]);
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writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
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break;
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}
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}
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void mtk_disp_mutex_enable(struct mtk_disp_mutex *mutex)
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{
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struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
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mutex[mutex->id]);
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WARN_ON(&ddp->mutex[mutex->id] != mutex);
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writel(1, ddp->regs + DISP_REG_MUTEX_EN(mutex->id));
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}
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void mtk_disp_mutex_disable(struct mtk_disp_mutex *mutex)
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{
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struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
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mutex[mutex->id]);
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WARN_ON(&ddp->mutex[mutex->id] != mutex);
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writel(0, ddp->regs + DISP_REG_MUTEX_EN(mutex->id));
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}
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void mtk_disp_mutex_acquire(struct mtk_disp_mutex *mutex)
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{
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struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
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mutex[mutex->id]);
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u32 tmp;
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writel(1, ddp->regs + DISP_REG_MUTEX_EN(mutex->id));
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writel(1, ddp->regs + DISP_REG_MUTEX(mutex->id));
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if (readl_poll_timeout_atomic(ddp->regs + DISP_REG_MUTEX(mutex->id),
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tmp, tmp & INT_MUTEX, 1, 10000))
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pr_err("could not acquire mutex %d\n", mutex->id);
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}
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void mtk_disp_mutex_release(struct mtk_disp_mutex *mutex)
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{
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struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
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mutex[mutex->id]);
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writel(0, ddp->regs + DISP_REG_MUTEX(mutex->id));
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}
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static int mtk_ddp_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mtk_ddp *ddp;
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struct resource *regs;
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int i;
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ddp = devm_kzalloc(dev, sizeof(*ddp), GFP_KERNEL);
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if (!ddp)
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return -ENOMEM;
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for (i = 0; i < 10; i++)
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ddp->mutex[i].id = i;
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ddp->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(ddp->clk)) {
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dev_err(dev, "Failed to get clock\n");
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return PTR_ERR(ddp->clk);
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}
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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ddp->regs = devm_ioremap_resource(dev, regs);
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if (IS_ERR(ddp->regs)) {
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dev_err(dev, "Failed to map mutex registers\n");
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return PTR_ERR(ddp->regs);
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}
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ddp->mutex_mod = of_device_get_match_data(dev);
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platform_set_drvdata(pdev, ddp);
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return 0;
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}
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static int mtk_ddp_remove(struct platform_device *pdev)
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{
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return 0;
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}
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static const struct of_device_id ddp_driver_dt_match[] = {
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{ .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod},
|
|
{ .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod},
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, ddp_driver_dt_match);
|
|
|
|
struct platform_driver mtk_ddp_driver = {
|
|
.probe = mtk_ddp_probe,
|
|
.remove = mtk_ddp_remove,
|
|
.driver = {
|
|
.name = "mediatek-ddp",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = ddp_driver_dt_match,
|
|
},
|
|
};
|