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c432a29d3f
isp iommu requires wrapper variants of the clocks.
noc variants are always on and using the wrapper variants will activate
{A,H}CLK_ISP{0,1} due to the hierarchy.
Tested using the pending isp patch set (which is not upstream
yet). Without this patch, streaming from the isp stalls.
Also add the respective power domain and remove the "disabled" status.
Refer:
RK3399 TRM v1.4 Fig. 2-4 RK3399 Clock Architecture Diagram
RK3399 TRM v1.4 Fig. 8-1 RK3399 Power Domain Partition
Signed-off-by: Helen Koike <helen.koike@collabora.com>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2658 lines
63 KiB
Plaintext
2658 lines
63 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
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*/
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#include <dt-bindings/clock/rk3399-cru.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/power/rk3399-power.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "rockchip,rk3399";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ethernet0 = &gmac;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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i2c7 = &i2c7;
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i2c8 = &i2c8;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu_l0>;
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};
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core1 {
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cpu = <&cpu_l1>;
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};
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core2 {
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cpu = <&cpu_l2>;
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};
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core3 {
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cpu = <&cpu_l3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu_b0>;
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};
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core1 {
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cpu = <&cpu_b1>;
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};
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};
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};
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cpu_l0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x0>;
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enable-method = "psci";
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capacity-dmips-mhz = <485>;
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clocks = <&cru ARMCLKL>;
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#cooling-cells = <2>; /* min followed by max */
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dynamic-power-coefficient = <100>;
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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};
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cpu_l1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x1>;
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enable-method = "psci";
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capacity-dmips-mhz = <485>;
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clocks = <&cru ARMCLKL>;
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#cooling-cells = <2>; /* min followed by max */
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dynamic-power-coefficient = <100>;
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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};
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cpu_l2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x2>;
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enable-method = "psci";
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capacity-dmips-mhz = <485>;
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clocks = <&cru ARMCLKL>;
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#cooling-cells = <2>; /* min followed by max */
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dynamic-power-coefficient = <100>;
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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};
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cpu_l3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x3>;
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enable-method = "psci";
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capacity-dmips-mhz = <485>;
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clocks = <&cru ARMCLKL>;
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#cooling-cells = <2>; /* min followed by max */
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dynamic-power-coefficient = <100>;
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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};
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cpu_b0: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0 0x100>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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clocks = <&cru ARMCLKB>;
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#cooling-cells = <2>; /* min followed by max */
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dynamic-power-coefficient = <436>;
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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};
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cpu_b1: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0 0x101>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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clocks = <&cru ARMCLKB>;
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#cooling-cells = <2>; /* min followed by max */
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dynamic-power-coefficient = <436>;
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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};
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idle-states {
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entry-method = "psci";
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CPU_SLEEP: cpu-sleep {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <120>;
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exit-latency-us = <250>;
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min-residency-us = <900>;
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};
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CLUSTER_SLEEP: cluster-sleep {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x1010000>;
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entry-latency-us = <400>;
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exit-latency-us = <500>;
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min-residency-us = <2000>;
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};
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};
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};
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display-subsystem {
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compatible = "rockchip,display-subsystem";
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ports = <&vopl_out>, <&vopb_out>;
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};
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pmu_a53 {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
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};
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pmu_a72 {
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compatible = "arm,cortex-a72-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
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arm,no-tick-in-suspend;
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};
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xin24m: xin24m {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dmac_bus: dma-controller@ff6d0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0xff6d0000 0x0 0x4000>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC0_PERILP>;
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clock-names = "apb_pclk";
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};
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dmac_peri: dma-controller@ff6e0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0xff6e0000 0x0 0x4000>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC1_PERILP>;
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clock-names = "apb_pclk";
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};
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};
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pcie0: pcie@f8000000 {
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compatible = "rockchip,rk3399-pcie";
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reg = <0x0 0xf8000000 0x0 0x2000000>,
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<0x0 0xfd000000 0x0 0x1000000>;
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reg-names = "axi-base", "apb-base";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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aspm-no-l0s;
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bus-range = <0x0 0x1f>;
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clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
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<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
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clock-names = "aclk", "aclk-perf",
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"hclk", "pm";
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "sys", "legacy", "client";
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie0_intc 0>,
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<0 0 0 2 &pcie0_intc 1>,
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<0 0 0 3 &pcie0_intc 2>,
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<0 0 0 4 &pcie0_intc 3>;
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linux,pci-domain = <0>;
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max-link-speed = <1>;
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msi-map = <0x0 &its 0x0 0x1000>;
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phys = <&pcie_phy 0>, <&pcie_phy 1>,
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<&pcie_phy 2>, <&pcie_phy 3>;
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phy-names = "pcie-phy-0", "pcie-phy-1",
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"pcie-phy-2", "pcie-phy-3";
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ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
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0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
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resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
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<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
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<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
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<&cru SRST_A_PCIE>;
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reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
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"pm", "pclk", "aclk";
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status = "disabled";
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pcie0_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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gmac: ethernet@fe300000 {
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compatible = "rockchip,rk3399-gmac";
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reg = <0x0 0xfe300000 0x0 0x10000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "macirq";
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clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
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<&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
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<&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
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<&cru PCLK_GMAC>;
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clock-names = "stmmaceth", "mac_clk_rx",
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"mac_clk_tx", "clk_mac_ref",
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"clk_mac_refout", "aclk_mac",
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"pclk_mac";
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power-domains = <&power RK3399_PD_GMAC>;
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resets = <&cru SRST_A_GMAC>;
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reset-names = "stmmaceth";
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rockchip,grf = <&grf>;
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status = "disabled";
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};
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sdio0: dwmmc@fe310000 {
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compatible = "rockchip,rk3399-dw-mshc",
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"rockchip,rk3288-dw-mshc";
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reg = <0x0 0xfe310000 0x0 0x4000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
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max-frequency = <150000000>;
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clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
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<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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power-domains = <&power RK3399_PD_SDIOAUDIO>;
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resets = <&cru SRST_SDIO0>;
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reset-names = "reset";
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status = "disabled";
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};
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sdmmc: dwmmc@fe320000 {
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compatible = "rockchip,rk3399-dw-mshc",
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"rockchip,rk3288-dw-mshc";
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reg = <0x0 0xfe320000 0x0 0x4000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
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max-frequency = <150000000>;
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assigned-clocks = <&cru HCLK_SD>;
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assigned-clock-rates = <200000000>;
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
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<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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power-domains = <&power RK3399_PD_SD>;
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resets = <&cru SRST_SDMMC>;
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reset-names = "reset";
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status = "disabled";
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};
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sdhci: sdhci@fe330000 {
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compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
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reg = <0x0 0xfe330000 0x0 0x10000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
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arasan,soc-ctl-syscon = <&grf>;
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assigned-clocks = <&cru SCLK_EMMC>;
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assigned-clock-rates = <200000000>;
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clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
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clock-names = "clk_xin", "clk_ahb";
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clock-output-names = "emmc_cardclock";
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#clock-cells = <0>;
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phys = <&emmc_phy>;
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phy-names = "phy_arasan";
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power-domains = <&power RK3399_PD_EMMC>;
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disable-cqe-dcmd;
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status = "disabled";
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};
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usb_host0_ehci: usb@fe380000 {
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compatible = "generic-ehci";
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reg = <0x0 0xfe380000 0x0 0x20000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
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<&u2phy0>;
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clock-names = "usbhost", "arbiter",
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"utmi";
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phys = <&u2phy0_host>;
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phy-names = "usb";
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status = "disabled";
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};
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usb_host0_ohci: usb@fe3a0000 {
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compatible = "generic-ohci";
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reg = <0x0 0xfe3a0000 0x0 0x20000>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
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<&u2phy0>;
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clock-names = "usbhost", "arbiter",
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"utmi";
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phys = <&u2phy0_host>;
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phy-names = "usb";
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status = "disabled";
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};
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usb_host1_ehci: usb@fe3c0000 {
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compatible = "generic-ehci";
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reg = <0x0 0xfe3c0000 0x0 0x20000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
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<&u2phy1>;
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clock-names = "usbhost", "arbiter",
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"utmi";
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phys = <&u2phy1_host>;
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phy-names = "usb";
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status = "disabled";
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};
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usb_host1_ohci: usb@fe3e0000 {
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compatible = "generic-ohci";
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reg = <0x0 0xfe3e0000 0x0 0x20000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
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<&u2phy1>;
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clock-names = "usbhost", "arbiter",
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"utmi";
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phys = <&u2phy1_host>;
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phy-names = "usb";
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status = "disabled";
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};
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usbdrd3_0: usb@fe800000 {
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compatible = "rockchip,rk3399-dwc3";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
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<&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
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<&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
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clock-names = "ref_clk", "suspend_clk",
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"bus_clk", "aclk_usb3_rksoc_axi_perf",
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"aclk_usb3", "grf_clk";
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resets = <&cru SRST_A_USB3_OTG0>;
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reset-names = "usb3-otg";
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status = "disabled";
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usbdrd_dwc3_0: dwc3 {
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compatible = "snps,dwc3";
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reg = <0x0 0xfe800000 0x0 0x100000>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
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dr_mode = "otg";
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phys = <&u2phy0_otg>, <&tcphy0_usb3>;
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phy-names = "usb2-phy", "usb3-phy";
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phy_type = "utmi_wide";
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snps,dis_enblslpm_quirk;
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snps,dis-u2-freeclk-exists-quirk;
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snps,dis_u2_susphy_quirk;
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snps,dis-del-phy-power-chg-quirk;
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snps,dis-tx-ipgap-linecheck-quirk;
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power-domains = <&power RK3399_PD_USB3>;
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status = "disabled";
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};
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};
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usbdrd3_1: usb@fe900000 {
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compatible = "rockchip,rk3399-dwc3";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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|
clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
|
|
<&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
|
|
<&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
|
|
clock-names = "ref_clk", "suspend_clk",
|
|
"bus_clk", "aclk_usb3_rksoc_axi_perf",
|
|
"aclk_usb3", "grf_clk";
|
|
resets = <&cru SRST_A_USB3_OTG1>;
|
|
reset-names = "usb3-otg";
|
|
status = "disabled";
|
|
|
|
usbdrd_dwc3_1: dwc3 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x0 0xfe900000 0x0 0x100000>;
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dr_mode = "otg";
|
|
phys = <&u2phy1_otg>, <&tcphy1_usb3>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
phy_type = "utmi_wide";
|
|
snps,dis_enblslpm_quirk;
|
|
snps,dis-u2-freeclk-exists-quirk;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis-del-phy-power-chg-quirk;
|
|
snps,dis-tx-ipgap-linecheck-quirk;
|
|
power-domains = <&power RK3399_PD_USB3>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
cdn_dp: dp@fec00000 {
|
|
compatible = "rockchip,rk3399-cdn-dp";
|
|
reg = <0x0 0xfec00000 0x0 0x100000>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
|
|
assigned-clock-rates = <100000000>, <200000000>;
|
|
clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
|
|
<&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
|
|
clock-names = "core-clk", "pclk", "spdif", "grf";
|
|
phys = <&tcphy0_dp>, <&tcphy1_dp>;
|
|
power-domains = <&power RK3399_PD_HDCP>;
|
|
resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
|
|
<&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
|
|
reset-names = "spdif", "dptx", "apb", "core";
|
|
rockchip,grf = <&grf>;
|
|
#sound-dai-cells = <1>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
dp_in: port {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
dp_in_vopb: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&vopb_out_dp>;
|
|
};
|
|
|
|
dp_in_vopl: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&vopl_out_dp>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
gic: interrupt-controller@fee00000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <4>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
interrupt-controller;
|
|
|
|
reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
|
|
<0x0 0xfef00000 0 0xc0000>, /* GICR */
|
|
<0x0 0xfff00000 0 0x10000>, /* GICC */
|
|
<0x0 0xfff10000 0 0x10000>, /* GICH */
|
|
<0x0 0xfff20000 0 0x10000>; /* GICV */
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
its: interrupt-controller@fee20000 {
|
|
compatible = "arm,gic-v3-its";
|
|
msi-controller;
|
|
reg = <0x0 0xfee20000 0x0 0x20000>;
|
|
};
|
|
|
|
ppi-partitions {
|
|
ppi_cluster0: interrupt-partition-0 {
|
|
affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
|
|
};
|
|
|
|
ppi_cluster1: interrupt-partition-1 {
|
|
affinity = <&cpu_b0 &cpu_b1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
saradc: saradc@ff100000 {
|
|
compatible = "rockchip,rk3399-saradc";
|
|
reg = <0x0 0xff100000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
#io-channel-cells = <1>;
|
|
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
|
|
clock-names = "saradc", "apb_pclk";
|
|
resets = <&cru SRST_P_SARADC>;
|
|
reset-names = "saradc-apb";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@ff110000 {
|
|
compatible = "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xff110000 0x0 0x1000>;
|
|
assigned-clocks = <&cru SCLK_I2C1>;
|
|
assigned-clock-rates = <200000000>;
|
|
clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@ff120000 {
|
|
compatible = "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xff120000 0x0 0x1000>;
|
|
assigned-clocks = <&cru SCLK_I2C2>;
|
|
assigned-clock-rates = <200000000>;
|
|
clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@ff130000 {
|
|
compatible = "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xff130000 0x0 0x1000>;
|
|
assigned-clocks = <&cru SCLK_I2C3>;
|
|
assigned-clock-rates = <200000000>;
|
|
clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@ff140000 {
|
|
compatible = "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xff140000 0x0 0x1000>;
|
|
assigned-clocks = <&cru SCLK_I2C5>;
|
|
assigned-clock-rates = <200000000>;
|
|
clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c5_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c6: i2c@ff150000 {
|
|
compatible = "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xff150000 0x0 0x1000>;
|
|
assigned-clocks = <&cru SCLK_I2C6>;
|
|
assigned-clock-rates = <200000000>;
|
|
clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c6_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c7: i2c@ff160000 {
|
|
compatible = "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xff160000 0x0 0x1000>;
|
|
assigned-clocks = <&cru SCLK_I2C7>;
|
|
assigned-clock-rates = <200000000>;
|
|
clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c7_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart0: serial@ff180000 {
|
|
compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xff180000 0x0 0x100>;
|
|
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart0_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@ff190000 {
|
|
compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xff190000 0x0 0x100>;
|
|
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart1_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@ff1a0000 {
|
|
compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xff1a0000 0x0 0x100>;
|
|
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart2c_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@ff1b0000 {
|
|
compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xff1b0000 0x0 0x100>;
|
|
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart3_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@ff1c0000 {
|
|
compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
|
|
reg = <0x0 0xff1c0000 0x0 0x1000>;
|
|
clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
|
|
clock-names = "spiclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dmac_peri 10>, <&dmac_peri 11>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@ff1d0000 {
|
|
compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
|
|
reg = <0x0 0xff1d0000 0x0 0x1000>;
|
|
clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
|
|
clock-names = "spiclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dmac_peri 12>, <&dmac_peri 13>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@ff1e0000 {
|
|
compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
|
|
reg = <0x0 0xff1e0000 0x0 0x1000>;
|
|
clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
|
|
clock-names = "spiclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dmac_peri 14>, <&dmac_peri 15>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi4: spi@ff1f0000 {
|
|
compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
|
|
reg = <0x0 0xff1f0000 0x0 0x1000>;
|
|
clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
|
|
clock-names = "spiclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dmac_peri 18>, <&dmac_peri 19>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi5: spi@ff200000 {
|
|
compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
|
|
reg = <0x0 0xff200000 0x0 0x1000>;
|
|
clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
|
|
clock-names = "spiclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dmac_bus 8>, <&dmac_bus 9>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
|
|
power-domains = <&power RK3399_PD_SDIOAUDIO>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
thermal_zones: thermal-zones {
|
|
cpu_thermal: cpu {
|
|
polling-delay-passive = <100>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsadc 0>;
|
|
|
|
trips {
|
|
cpu_alert0: cpu_alert0 {
|
|
temperature = <70000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
cpu_alert1: cpu_alert1 {
|
|
temperature = <75000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
cpu_crit: cpu_crit {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu_alert0>;
|
|
cooling-device =
|
|
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
map1 {
|
|
trip = <&cpu_alert1>;
|
|
cooling-device =
|
|
<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpu_thermal: gpu {
|
|
polling-delay-passive = <100>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsadc 1>;
|
|
|
|
trips {
|
|
gpu_alert0: gpu_alert0 {
|
|
temperature = <75000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
gpu_crit: gpu_crit {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&gpu_alert0>;
|
|
cooling-device =
|
|
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tsadc: tsadc@ff260000 {
|
|
compatible = "rockchip,rk3399-tsadc";
|
|
reg = <0x0 0xff260000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
assigned-clocks = <&cru SCLK_TSADC>;
|
|
assigned-clock-rates = <750000>;
|
|
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
|
|
clock-names = "tsadc", "apb_pclk";
|
|
resets = <&cru SRST_TSADC>;
|
|
reset-names = "tsadc-apb";
|
|
rockchip,grf = <&grf>;
|
|
rockchip,hw-tshut-temp = <95000>;
|
|
pinctrl-names = "init", "default", "sleep";
|
|
pinctrl-0 = <&otp_gpio>;
|
|
pinctrl-1 = <&otp_out>;
|
|
pinctrl-2 = <&otp_gpio>;
|
|
#thermal-sensor-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qos_emmc: qos@ffa58000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffa58000 0x0 0x20>;
|
|
};
|
|
|
|
qos_gmac: qos@ffa5c000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffa5c000 0x0 0x20>;
|
|
};
|
|
|
|
qos_pcie: qos@ffa60080 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffa60080 0x0 0x20>;
|
|
};
|
|
|
|
qos_usb_host0: qos@ffa60100 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffa60100 0x0 0x20>;
|
|
};
|
|
|
|
qos_usb_host1: qos@ffa60180 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffa60180 0x0 0x20>;
|
|
};
|
|
|
|
qos_usb_otg0: qos@ffa70000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffa70000 0x0 0x20>;
|
|
};
|
|
|
|
qos_usb_otg1: qos@ffa70080 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffa70080 0x0 0x20>;
|
|
};
|
|
|
|
qos_sd: qos@ffa74000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffa74000 0x0 0x20>;
|
|
};
|
|
|
|
qos_sdioaudio: qos@ffa76000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffa76000 0x0 0x20>;
|
|
};
|
|
|
|
qos_hdcp: qos@ffa90000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffa90000 0x0 0x20>;
|
|
};
|
|
|
|
qos_iep: qos@ffa98000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffa98000 0x0 0x20>;
|
|
};
|
|
|
|
qos_isp0_m0: qos@ffaa0000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffaa0000 0x0 0x20>;
|
|
};
|
|
|
|
qos_isp0_m1: qos@ffaa0080 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffaa0080 0x0 0x20>;
|
|
};
|
|
|
|
qos_isp1_m0: qos@ffaa8000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffaa8000 0x0 0x20>;
|
|
};
|
|
|
|
qos_isp1_m1: qos@ffaa8080 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffaa8080 0x0 0x20>;
|
|
};
|
|
|
|
qos_rga_r: qos@ffab0000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffab0000 0x0 0x20>;
|
|
};
|
|
|
|
qos_rga_w: qos@ffab0080 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffab0080 0x0 0x20>;
|
|
};
|
|
|
|
qos_video_m0: qos@ffab8000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffab8000 0x0 0x20>;
|
|
};
|
|
|
|
qos_video_m1_r: qos@ffac0000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffac0000 0x0 0x20>;
|
|
};
|
|
|
|
qos_video_m1_w: qos@ffac0080 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffac0080 0x0 0x20>;
|
|
};
|
|
|
|
qos_vop_big_r: qos@ffac8000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffac8000 0x0 0x20>;
|
|
};
|
|
|
|
qos_vop_big_w: qos@ffac8080 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffac8080 0x0 0x20>;
|
|
};
|
|
|
|
qos_vop_little: qos@ffad0000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffad0000 0x0 0x20>;
|
|
};
|
|
|
|
qos_perihp: qos@ffad8080 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffad8080 0x0 0x20>;
|
|
};
|
|
|
|
qos_gpu: qos@ffae0000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffae0000 0x0 0x20>;
|
|
};
|
|
|
|
pmu: power-management@ff310000 {
|
|
compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
|
|
reg = <0x0 0xff310000 0x0 0x1000>;
|
|
|
|
/*
|
|
* Note: RK3399 supports 6 voltage domains including VD_CORE_L,
|
|
* VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
|
|
* Some of the power domains are grouped together for every
|
|
* voltage domain.
|
|
* The detail contents as below.
|
|
*/
|
|
power: power-controller {
|
|
compatible = "rockchip,rk3399-power-controller";
|
|
#power-domain-cells = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
/* These power domains are grouped by VD_CENTER */
|
|
pd_iep@RK3399_PD_IEP {
|
|
reg = <RK3399_PD_IEP>;
|
|
clocks = <&cru ACLK_IEP>,
|
|
<&cru HCLK_IEP>;
|
|
pm_qos = <&qos_iep>;
|
|
};
|
|
pd_rga@RK3399_PD_RGA {
|
|
reg = <RK3399_PD_RGA>;
|
|
clocks = <&cru ACLK_RGA>,
|
|
<&cru HCLK_RGA>;
|
|
pm_qos = <&qos_rga_r>,
|
|
<&qos_rga_w>;
|
|
};
|
|
pd_vcodec@RK3399_PD_VCODEC {
|
|
reg = <RK3399_PD_VCODEC>;
|
|
clocks = <&cru ACLK_VCODEC>,
|
|
<&cru HCLK_VCODEC>;
|
|
pm_qos = <&qos_video_m0>;
|
|
};
|
|
pd_vdu@RK3399_PD_VDU {
|
|
reg = <RK3399_PD_VDU>;
|
|
clocks = <&cru ACLK_VDU>,
|
|
<&cru HCLK_VDU>;
|
|
pm_qos = <&qos_video_m1_r>,
|
|
<&qos_video_m1_w>;
|
|
};
|
|
|
|
/* These power domains are grouped by VD_GPU */
|
|
pd_gpu@RK3399_PD_GPU {
|
|
reg = <RK3399_PD_GPU>;
|
|
clocks = <&cru ACLK_GPU>;
|
|
pm_qos = <&qos_gpu>;
|
|
};
|
|
|
|
/* These power domains are grouped by VD_LOGIC */
|
|
pd_edp@RK3399_PD_EDP {
|
|
reg = <RK3399_PD_EDP>;
|
|
clocks = <&cru PCLK_EDP_CTRL>;
|
|
};
|
|
pd_emmc@RK3399_PD_EMMC {
|
|
reg = <RK3399_PD_EMMC>;
|
|
clocks = <&cru ACLK_EMMC>;
|
|
pm_qos = <&qos_emmc>;
|
|
};
|
|
pd_gmac@RK3399_PD_GMAC {
|
|
reg = <RK3399_PD_GMAC>;
|
|
clocks = <&cru ACLK_GMAC>,
|
|
<&cru PCLK_GMAC>;
|
|
pm_qos = <&qos_gmac>;
|
|
};
|
|
pd_sd@RK3399_PD_SD {
|
|
reg = <RK3399_PD_SD>;
|
|
clocks = <&cru HCLK_SDMMC>,
|
|
<&cru SCLK_SDMMC>;
|
|
pm_qos = <&qos_sd>;
|
|
};
|
|
pd_sdioaudio@RK3399_PD_SDIOAUDIO {
|
|
reg = <RK3399_PD_SDIOAUDIO>;
|
|
clocks = <&cru HCLK_SDIO>;
|
|
pm_qos = <&qos_sdioaudio>;
|
|
};
|
|
pd_usb3@RK3399_PD_USB3 {
|
|
reg = <RK3399_PD_USB3>;
|
|
clocks = <&cru ACLK_USB3>;
|
|
pm_qos = <&qos_usb_otg0>,
|
|
<&qos_usb_otg1>;
|
|
};
|
|
pd_vio@RK3399_PD_VIO {
|
|
reg = <RK3399_PD_VIO>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
pd_hdcp@RK3399_PD_HDCP {
|
|
reg = <RK3399_PD_HDCP>;
|
|
clocks = <&cru ACLK_HDCP>,
|
|
<&cru HCLK_HDCP>,
|
|
<&cru PCLK_HDCP>;
|
|
pm_qos = <&qos_hdcp>;
|
|
};
|
|
pd_isp0@RK3399_PD_ISP0 {
|
|
reg = <RK3399_PD_ISP0>;
|
|
clocks = <&cru ACLK_ISP0>,
|
|
<&cru HCLK_ISP0>;
|
|
pm_qos = <&qos_isp0_m0>,
|
|
<&qos_isp0_m1>;
|
|
};
|
|
pd_isp1@RK3399_PD_ISP1 {
|
|
reg = <RK3399_PD_ISP1>;
|
|
clocks = <&cru ACLK_ISP1>,
|
|
<&cru HCLK_ISP1>;
|
|
pm_qos = <&qos_isp1_m0>,
|
|
<&qos_isp1_m1>;
|
|
};
|
|
pd_tcpc0@RK3399_PD_TCPC0 {
|
|
reg = <RK3399_PD_TCPD0>;
|
|
clocks = <&cru SCLK_UPHY0_TCPDCORE>,
|
|
<&cru SCLK_UPHY0_TCPDPHY_REF>;
|
|
};
|
|
pd_tcpc1@RK3399_PD_TCPC1 {
|
|
reg = <RK3399_PD_TCPD1>;
|
|
clocks = <&cru SCLK_UPHY1_TCPDCORE>,
|
|
<&cru SCLK_UPHY1_TCPDPHY_REF>;
|
|
};
|
|
pd_vo@RK3399_PD_VO {
|
|
reg = <RK3399_PD_VO>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
pd_vopb@RK3399_PD_VOPB {
|
|
reg = <RK3399_PD_VOPB>;
|
|
clocks = <&cru ACLK_VOP0>,
|
|
<&cru HCLK_VOP0>;
|
|
pm_qos = <&qos_vop_big_r>,
|
|
<&qos_vop_big_w>;
|
|
};
|
|
pd_vopl@RK3399_PD_VOPL {
|
|
reg = <RK3399_PD_VOPL>;
|
|
clocks = <&cru ACLK_VOP1>,
|
|
<&cru HCLK_VOP1>;
|
|
pm_qos = <&qos_vop_little>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
pmugrf: syscon@ff320000 {
|
|
compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
|
|
reg = <0x0 0xff320000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
pmu_io_domains: io-domains {
|
|
compatible = "rockchip,rk3399-pmu-io-voltage-domain";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
spi3: spi@ff350000 {
|
|
compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
|
|
reg = <0x0 0xff350000 0x0 0x1000>;
|
|
clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
|
|
clock-names = "spiclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@ff370000 {
|
|
compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xff370000 0x0 0x100>;
|
|
clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart4_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@ff3c0000 {
|
|
compatible = "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xff3c0000 0x0 0x1000>;
|
|
assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
|
|
assigned-clock-rates = <200000000>;
|
|
clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@ff3d0000 {
|
|
compatible = "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xff3d0000 0x0 0x1000>;
|
|
assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
|
|
assigned-clock-rates = <200000000>;
|
|
clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c8: i2c@ff3e0000 {
|
|
compatible = "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xff3e0000 0x0 0x1000>;
|
|
assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
|
|
assigned-clock-rates = <200000000>;
|
|
clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c8_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm0: pwm@ff420000 {
|
|
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
|
|
reg = <0x0 0xff420000 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm0_pin>;
|
|
clocks = <&pmucru PCLK_RKPWM_PMU>;
|
|
clock-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@ff420010 {
|
|
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
|
|
reg = <0x0 0xff420010 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm1_pin>;
|
|
clocks = <&pmucru PCLK_RKPWM_PMU>;
|
|
clock-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@ff420020 {
|
|
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
|
|
reg = <0x0 0xff420020 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm2_pin>;
|
|
clocks = <&pmucru PCLK_RKPWM_PMU>;
|
|
clock-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@ff420030 {
|
|
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
|
|
reg = <0x0 0xff420030 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm3a_pin>;
|
|
clocks = <&pmucru PCLK_RKPWM_PMU>;
|
|
clock-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
vpu: video-codec@ff650000 {
|
|
compatible = "rockchip,rk3399-vpu";
|
|
reg = <0x0 0xff650000 0x0 0x800>;
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "vepu", "vdpu";
|
|
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
|
|
clock-names = "aclk", "hclk";
|
|
iommus = <&vpu_mmu>;
|
|
power-domains = <&power RK3399_PD_VCODEC>;
|
|
};
|
|
|
|
vpu_mmu: iommu@ff650800 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x0 0xff650800 0x0 0x40>;
|
|
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "vpu_mmu";
|
|
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
|
|
clock-names = "aclk", "iface";
|
|
#iommu-cells = <0>;
|
|
power-domains = <&power RK3399_PD_VCODEC>;
|
|
};
|
|
|
|
vdec_mmu: iommu@ff660480 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
|
|
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "vdec_mmu";
|
|
clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
|
|
clock-names = "aclk", "iface";
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
iep_mmu: iommu@ff670800 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x0 0xff670800 0x0 0x40>;
|
|
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "iep_mmu";
|
|
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
|
|
clock-names = "aclk", "iface";
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rga: rga@ff680000 {
|
|
compatible = "rockchip,rk3399-rga";
|
|
reg = <0x0 0xff680000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
|
|
clock-names = "aclk", "hclk", "sclk";
|
|
resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
|
|
reset-names = "core", "axi", "ahb";
|
|
power-domains = <&power RK3399_PD_RGA>;
|
|
};
|
|
|
|
efuse0: efuse@ff690000 {
|
|
compatible = "rockchip,rk3399-efuse";
|
|
reg = <0x0 0xff690000 0x0 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
clocks = <&cru PCLK_EFUSE1024NS>;
|
|
clock-names = "pclk_efuse";
|
|
|
|
/* Data cells */
|
|
cpu_id: cpu-id@7 {
|
|
reg = <0x07 0x10>;
|
|
};
|
|
cpub_leakage: cpu-leakage@17 {
|
|
reg = <0x17 0x1>;
|
|
};
|
|
gpu_leakage: gpu-leakage@18 {
|
|
reg = <0x18 0x1>;
|
|
};
|
|
center_leakage: center-leakage@19 {
|
|
reg = <0x19 0x1>;
|
|
};
|
|
cpul_leakage: cpu-leakage@1a {
|
|
reg = <0x1a 0x1>;
|
|
};
|
|
logic_leakage: logic-leakage@1b {
|
|
reg = <0x1b 0x1>;
|
|
};
|
|
wafer_info: wafer-info@1c {
|
|
reg = <0x1c 0x1>;
|
|
};
|
|
};
|
|
|
|
pmucru: pmu-clock-controller@ff750000 {
|
|
compatible = "rockchip,rk3399-pmucru";
|
|
reg = <0x0 0xff750000 0x0 0x1000>;
|
|
rockchip,grf = <&pmugrf>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
assigned-clocks = <&pmucru PLL_PPLL>;
|
|
assigned-clock-rates = <676000000>;
|
|
};
|
|
|
|
cru: clock-controller@ff760000 {
|
|
compatible = "rockchip,rk3399-cru";
|
|
reg = <0x0 0xff760000 0x0 0x1000>;
|
|
rockchip,grf = <&grf>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
assigned-clocks =
|
|
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
|
|
<&cru PLL_NPLL>,
|
|
<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
|
|
<&cru PCLK_PERIHP>,
|
|
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
|
|
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
|
|
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
|
|
<&cru ACLK_VIO>, <&cru ACLK_HDCP>,
|
|
<&cru ACLK_GIC_PRE>,
|
|
<&cru PCLK_DDR>;
|
|
assigned-clock-rates =
|
|
<594000000>, <800000000>,
|
|
<1000000000>,
|
|
<150000000>, <75000000>,
|
|
<37500000>,
|
|
<100000000>, <100000000>,
|
|
<50000000>, <600000000>,
|
|
<100000000>, <50000000>,
|
|
<400000000>, <400000000>,
|
|
<200000000>,
|
|
<200000000>;
|
|
};
|
|
|
|
grf: syscon@ff770000 {
|
|
compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
|
|
reg = <0x0 0xff770000 0x0 0x10000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
io_domains: io-domains {
|
|
compatible = "rockchip,rk3399-io-voltage-domain";
|
|
status = "disabled";
|
|
};
|
|
|
|
u2phy0: usb2-phy@e450 {
|
|
compatible = "rockchip,rk3399-usb2phy";
|
|
reg = <0xe450 0x10>;
|
|
clocks = <&cru SCLK_USB2PHY0_REF>;
|
|
clock-names = "phyclk";
|
|
#clock-cells = <0>;
|
|
clock-output-names = "clk_usbphy0_480m";
|
|
status = "disabled";
|
|
|
|
u2phy0_host: host-port {
|
|
#phy-cells = <0>;
|
|
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "linestate";
|
|
status = "disabled";
|
|
};
|
|
|
|
u2phy0_otg: otg-port {
|
|
#phy-cells = <0>;
|
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "otg-bvalid", "otg-id",
|
|
"linestate";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
u2phy1: usb2-phy@e460 {
|
|
compatible = "rockchip,rk3399-usb2phy";
|
|
reg = <0xe460 0x10>;
|
|
clocks = <&cru SCLK_USB2PHY1_REF>;
|
|
clock-names = "phyclk";
|
|
#clock-cells = <0>;
|
|
clock-output-names = "clk_usbphy1_480m";
|
|
status = "disabled";
|
|
|
|
u2phy1_host: host-port {
|
|
#phy-cells = <0>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "linestate";
|
|
status = "disabled";
|
|
};
|
|
|
|
u2phy1_otg: otg-port {
|
|
#phy-cells = <0>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "otg-bvalid", "otg-id",
|
|
"linestate";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
emmc_phy: phy@f780 {
|
|
compatible = "rockchip,rk3399-emmc-phy";
|
|
reg = <0xf780 0x24>;
|
|
clocks = <&sdhci>;
|
|
clock-names = "emmcclk";
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie_phy: pcie-phy {
|
|
compatible = "rockchip,rk3399-pcie-phy";
|
|
clocks = <&cru SCLK_PCIEPHY_REF>;
|
|
clock-names = "refclk";
|
|
#phy-cells = <1>;
|
|
resets = <&cru SRST_PCIEPHY>;
|
|
drive-impedance-ohm = <50>;
|
|
reset-names = "phy";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
tcphy0: phy@ff7c0000 {
|
|
compatible = "rockchip,rk3399-typec-phy";
|
|
reg = <0x0 0xff7c0000 0x0 0x40000>;
|
|
clocks = <&cru SCLK_UPHY0_TCPDCORE>,
|
|
<&cru SCLK_UPHY0_TCPDPHY_REF>;
|
|
clock-names = "tcpdcore", "tcpdphy-ref";
|
|
assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
|
|
assigned-clock-rates = <50000000>;
|
|
power-domains = <&power RK3399_PD_TCPD0>;
|
|
resets = <&cru SRST_UPHY0>,
|
|
<&cru SRST_UPHY0_PIPE_L00>,
|
|
<&cru SRST_P_UPHY0_TCPHY>;
|
|
reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
|
|
rockchip,grf = <&grf>;
|
|
status = "disabled";
|
|
|
|
tcphy0_dp: dp-port {
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
tcphy0_usb3: usb3-port {
|
|
#phy-cells = <0>;
|
|
};
|
|
};
|
|
|
|
tcphy1: phy@ff800000 {
|
|
compatible = "rockchip,rk3399-typec-phy";
|
|
reg = <0x0 0xff800000 0x0 0x40000>;
|
|
clocks = <&cru SCLK_UPHY1_TCPDCORE>,
|
|
<&cru SCLK_UPHY1_TCPDPHY_REF>;
|
|
clock-names = "tcpdcore", "tcpdphy-ref";
|
|
assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
|
|
assigned-clock-rates = <50000000>;
|
|
power-domains = <&power RK3399_PD_TCPD1>;
|
|
resets = <&cru SRST_UPHY1>,
|
|
<&cru SRST_UPHY1_PIPE_L00>,
|
|
<&cru SRST_P_UPHY1_TCPHY>;
|
|
reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
|
|
rockchip,grf = <&grf>;
|
|
status = "disabled";
|
|
|
|
tcphy1_dp: dp-port {
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
tcphy1_usb3: usb3-port {
|
|
#phy-cells = <0>;
|
|
};
|
|
};
|
|
|
|
watchdog@ff848000 {
|
|
compatible = "snps,dw-wdt";
|
|
reg = <0x0 0xff848000 0x0 0x100>;
|
|
clocks = <&cru PCLK_WDT>;
|
|
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
};
|
|
|
|
rktimer: rktimer@ff850000 {
|
|
compatible = "rockchip,rk3399-timer";
|
|
reg = <0x0 0xff850000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
|
|
clock-names = "pclk", "timer";
|
|
};
|
|
|
|
spdif: spdif@ff870000 {
|
|
compatible = "rockchip,rk3399-spdif";
|
|
reg = <0x0 0xff870000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dmac_bus 7>;
|
|
dma-names = "tx";
|
|
clock-names = "mclk", "hclk";
|
|
clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spdif_bus>;
|
|
power-domains = <&power RK3399_PD_SDIOAUDIO>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s0: i2s@ff880000 {
|
|
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
|
|
reg = <0x0 0xff880000 0x0 0x1000>;
|
|
rockchip,grf = <&grf>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dmac_bus 0>, <&dmac_bus 1>;
|
|
dma-names = "tx", "rx";
|
|
clock-names = "i2s_clk", "i2s_hclk";
|
|
clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s0_8ch_bus>;
|
|
power-domains = <&power RK3399_PD_SDIOAUDIO>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s1: i2s@ff890000 {
|
|
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
|
|
reg = <0x0 0xff890000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dmac_bus 2>, <&dmac_bus 3>;
|
|
dma-names = "tx", "rx";
|
|
clock-names = "i2s_clk", "i2s_hclk";
|
|
clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s1_2ch_bus>;
|
|
power-domains = <&power RK3399_PD_SDIOAUDIO>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s2: i2s@ff8a0000 {
|
|
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
|
|
reg = <0x0 0xff8a0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dmac_bus 4>, <&dmac_bus 5>;
|
|
dma-names = "tx", "rx";
|
|
clock-names = "i2s_clk", "i2s_hclk";
|
|
clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
|
|
power-domains = <&power RK3399_PD_SDIOAUDIO>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vopl: vop@ff8f0000 {
|
|
compatible = "rockchip,rk3399-vop-lit";
|
|
reg = <0x0 0xff8f0000 0x0 0x3efc>;
|
|
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
|
|
assigned-clock-rates = <400000000>, <100000000>;
|
|
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
|
|
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
|
|
iommus = <&vopl_mmu>;
|
|
power-domains = <&power RK3399_PD_VOPL>;
|
|
resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
|
|
reset-names = "axi", "ahb", "dclk";
|
|
status = "disabled";
|
|
|
|
vopl_out: port {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
vopl_out_mipi: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&mipi_in_vopl>;
|
|
};
|
|
|
|
vopl_out_edp: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&edp_in_vopl>;
|
|
};
|
|
|
|
vopl_out_hdmi: endpoint@2 {
|
|
reg = <2>;
|
|
remote-endpoint = <&hdmi_in_vopl>;
|
|
};
|
|
|
|
vopl_out_mipi1: endpoint@3 {
|
|
reg = <3>;
|
|
remote-endpoint = <&mipi1_in_vopl>;
|
|
};
|
|
|
|
vopl_out_dp: endpoint@4 {
|
|
reg = <4>;
|
|
remote-endpoint = <&dp_in_vopl>;
|
|
};
|
|
};
|
|
};
|
|
|
|
vopl_mmu: iommu@ff8f3f00 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x0 0xff8f3f00 0x0 0x100>;
|
|
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "vopl_mmu";
|
|
clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3399_PD_VOPL>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vopb: vop@ff900000 {
|
|
compatible = "rockchip,rk3399-vop-big";
|
|
reg = <0x0 0xff900000 0x0 0x3efc>;
|
|
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
|
|
assigned-clock-rates = <400000000>, <100000000>;
|
|
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
|
|
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
|
|
iommus = <&vopb_mmu>;
|
|
power-domains = <&power RK3399_PD_VOPB>;
|
|
resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
|
|
reset-names = "axi", "ahb", "dclk";
|
|
status = "disabled";
|
|
|
|
vopb_out: port {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
vopb_out_edp: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&edp_in_vopb>;
|
|
};
|
|
|
|
vopb_out_mipi: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&mipi_in_vopb>;
|
|
};
|
|
|
|
vopb_out_hdmi: endpoint@2 {
|
|
reg = <2>;
|
|
remote-endpoint = <&hdmi_in_vopb>;
|
|
};
|
|
|
|
vopb_out_mipi1: endpoint@3 {
|
|
reg = <3>;
|
|
remote-endpoint = <&mipi1_in_vopb>;
|
|
};
|
|
|
|
vopb_out_dp: endpoint@4 {
|
|
reg = <4>;
|
|
remote-endpoint = <&dp_in_vopb>;
|
|
};
|
|
};
|
|
};
|
|
|
|
vopb_mmu: iommu@ff903f00 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x0 0xff903f00 0x0 0x100>;
|
|
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "vopb_mmu";
|
|
clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3399_PD_VOPB>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
isp0_mmu: iommu@ff914000 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "isp0_mmu";
|
|
clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
|
|
clock-names = "aclk", "iface";
|
|
#iommu-cells = <0>;
|
|
power-domains = <&power RK3399_PD_ISP0>;
|
|
rockchip,disable-mmu-reset;
|
|
};
|
|
|
|
isp1_mmu: iommu@ff924000 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "isp1_mmu";
|
|
clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
|
|
clock-names = "aclk", "iface";
|
|
#iommu-cells = <0>;
|
|
power-domains = <&power RK3399_PD_ISP1>;
|
|
rockchip,disable-mmu-reset;
|
|
};
|
|
|
|
hdmi_sound: hdmi-sound {
|
|
compatible = "simple-audio-card";
|
|
simple-audio-card,format = "i2s";
|
|
simple-audio-card,mclk-fs = <256>;
|
|
simple-audio-card,name = "hdmi-sound";
|
|
status = "disabled";
|
|
|
|
simple-audio-card,cpu {
|
|
sound-dai = <&i2s2>;
|
|
};
|
|
simple-audio-card,codec {
|
|
sound-dai = <&hdmi>;
|
|
};
|
|
};
|
|
|
|
hdmi: hdmi@ff940000 {
|
|
compatible = "rockchip,rk3399-dw-hdmi";
|
|
reg = <0x0 0xff940000 0x0 0x20000>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&cru PCLK_HDMI_CTRL>,
|
|
<&cru SCLK_HDMI_SFR>,
|
|
<&cru PLL_VPLL>,
|
|
<&cru PCLK_VIO_GRF>,
|
|
<&cru SCLK_HDMI_CEC>;
|
|
clock-names = "iahb", "isfr", "vpll", "grf", "cec";
|
|
power-domains = <&power RK3399_PD_HDCP>;
|
|
reg-io-width = <4>;
|
|
rockchip,grf = <&grf>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
hdmi_in: port {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
hdmi_in_vopb: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&vopb_out_hdmi>;
|
|
};
|
|
hdmi_in_vopl: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&vopl_out_hdmi>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
mipi_dsi: mipi@ff960000 {
|
|
compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
|
|
reg = <0x0 0xff960000 0x0 0x8000>;
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
|
|
<&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
|
|
clock-names = "ref", "pclk", "phy_cfg", "grf";
|
|
power-domains = <&power RK3399_PD_VIO>;
|
|
resets = <&cru SRST_P_MIPI_DSI0>;
|
|
reset-names = "apb";
|
|
rockchip,grf = <&grf>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
mipi_in: port@0 {
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
mipi_in_vopb: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&vopb_out_mipi>;
|
|
};
|
|
mipi_in_vopl: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&vopl_out_mipi>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
mipi_dsi1: mipi@ff968000 {
|
|
compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
|
|
reg = <0x0 0xff968000 0x0 0x8000>;
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
|
|
<&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
|
|
clock-names = "ref", "pclk", "phy_cfg", "grf";
|
|
power-domains = <&power RK3399_PD_VIO>;
|
|
resets = <&cru SRST_P_MIPI_DSI1>;
|
|
reset-names = "apb";
|
|
rockchip,grf = <&grf>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
mipi1_in: port@0 {
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
mipi1_in_vopb: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&vopb_out_mipi1>;
|
|
};
|
|
|
|
mipi1_in_vopl: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&vopl_out_mipi1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
edp: edp@ff970000 {
|
|
compatible = "rockchip,rk3399-edp";
|
|
reg = <0x0 0xff970000 0x0 0x8000>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
|
|
clock-names = "dp", "pclk", "grf";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&edp_hpd>;
|
|
power-domains = <&power RK3399_PD_EDP>;
|
|
resets = <&cru SRST_P_EDP_CTRL>;
|
|
reset-names = "dp";
|
|
rockchip,grf = <&grf>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
edp_in: port@0 {
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
edp_in_vopb: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&vopb_out_edp>;
|
|
};
|
|
|
|
edp_in_vopl: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&vopl_out_edp>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
gpu: gpu@ff9a0000 {
|
|
compatible = "rockchip,rk3399-mali", "arm,mali-t860";
|
|
reg = <0x0 0xff9a0000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "gpu", "job", "mmu";
|
|
clocks = <&cru ACLK_GPU>;
|
|
power-domains = <&power RK3399_PD_GPU>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "rockchip,rk3399-pinctrl";
|
|
rockchip,grf = <&grf>;
|
|
rockchip,pmu = <&pmugrf>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
gpio0: gpio0@ff720000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff720000 0x0 0x100>;
|
|
clocks = <&pmucru PCLK_GPIO0_PMU>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <0x2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x2>;
|
|
};
|
|
|
|
gpio1: gpio1@ff730000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff730000 0x0 0x100>;
|
|
clocks = <&pmucru PCLK_GPIO1_PMU>;
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <0x2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x2>;
|
|
};
|
|
|
|
gpio2: gpio2@ff780000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff780000 0x0 0x100>;
|
|
clocks = <&cru PCLK_GPIO2>;
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <0x2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x2>;
|
|
};
|
|
|
|
gpio3: gpio3@ff788000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff788000 0x0 0x100>;
|
|
clocks = <&cru PCLK_GPIO3>;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <0x2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x2>;
|
|
};
|
|
|
|
gpio4: gpio4@ff790000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff790000 0x0 0x100>;
|
|
clocks = <&cru PCLK_GPIO4>;
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <0x2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x2>;
|
|
};
|
|
|
|
pcfg_pull_up: pcfg-pull-up {
|
|
bias-pull-up;
|
|
};
|
|
|
|
pcfg_pull_down: pcfg-pull-down {
|
|
bias-pull-down;
|
|
};
|
|
|
|
pcfg_pull_none: pcfg-pull-none {
|
|
bias-disable;
|
|
};
|
|
|
|
pcfg_pull_none_12ma: pcfg-pull-none-12ma {
|
|
bias-disable;
|
|
drive-strength = <12>;
|
|
};
|
|
|
|
pcfg_pull_none_13ma: pcfg-pull-none-13ma {
|
|
bias-disable;
|
|
drive-strength = <13>;
|
|
};
|
|
|
|
pcfg_pull_none_18ma: pcfg-pull-none-18ma {
|
|
bias-disable;
|
|
drive-strength = <18>;
|
|
};
|
|
|
|
pcfg_pull_none_20ma: pcfg-pull-none-20ma {
|
|
bias-disable;
|
|
drive-strength = <20>;
|
|
};
|
|
|
|
pcfg_pull_up_2ma: pcfg-pull-up-2ma {
|
|
bias-pull-up;
|
|
drive-strength = <2>;
|
|
};
|
|
|
|
pcfg_pull_up_8ma: pcfg-pull-up-8ma {
|
|
bias-pull-up;
|
|
drive-strength = <8>;
|
|
};
|
|
|
|
pcfg_pull_up_18ma: pcfg-pull-up-18ma {
|
|
bias-pull-up;
|
|
drive-strength = <18>;
|
|
};
|
|
|
|
pcfg_pull_up_20ma: pcfg-pull-up-20ma {
|
|
bias-pull-up;
|
|
drive-strength = <20>;
|
|
};
|
|
|
|
pcfg_pull_down_4ma: pcfg-pull-down-4ma {
|
|
bias-pull-down;
|
|
drive-strength = <4>;
|
|
};
|
|
|
|
pcfg_pull_down_8ma: pcfg-pull-down-8ma {
|
|
bias-pull-down;
|
|
drive-strength = <8>;
|
|
};
|
|
|
|
pcfg_pull_down_12ma: pcfg-pull-down-12ma {
|
|
bias-pull-down;
|
|
drive-strength = <12>;
|
|
};
|
|
|
|
pcfg_pull_down_18ma: pcfg-pull-down-18ma {
|
|
bias-pull-down;
|
|
drive-strength = <18>;
|
|
};
|
|
|
|
pcfg_pull_down_20ma: pcfg-pull-down-20ma {
|
|
bias-pull-down;
|
|
drive-strength = <20>;
|
|
};
|
|
|
|
pcfg_output_high: pcfg-output-high {
|
|
output-high;
|
|
};
|
|
|
|
pcfg_output_low: pcfg-output-low {
|
|
output-low;
|
|
};
|
|
|
|
clock {
|
|
clk_32k: clk-32k {
|
|
rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
edp {
|
|
edp_hpd: edp-hpd {
|
|
rockchip,pins =
|
|
<4 RK_PC7 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
gmac {
|
|
rgmii_pins: rgmii-pins {
|
|
rockchip,pins =
|
|
/* mac_txclk */
|
|
<3 RK_PC1 1 &pcfg_pull_none_13ma>,
|
|
/* mac_rxclk */
|
|
<3 RK_PB6 1 &pcfg_pull_none>,
|
|
/* mac_mdio */
|
|
<3 RK_PB5 1 &pcfg_pull_none>,
|
|
/* mac_txen */
|
|
<3 RK_PB4 1 &pcfg_pull_none_13ma>,
|
|
/* mac_clk */
|
|
<3 RK_PB3 1 &pcfg_pull_none>,
|
|
/* mac_rxdv */
|
|
<3 RK_PB1 1 &pcfg_pull_none>,
|
|
/* mac_mdc */
|
|
<3 RK_PB0 1 &pcfg_pull_none>,
|
|
/* mac_rxd1 */
|
|
<3 RK_PA7 1 &pcfg_pull_none>,
|
|
/* mac_rxd0 */
|
|
<3 RK_PA6 1 &pcfg_pull_none>,
|
|
/* mac_txd1 */
|
|
<3 RK_PA5 1 &pcfg_pull_none_13ma>,
|
|
/* mac_txd0 */
|
|
<3 RK_PA4 1 &pcfg_pull_none_13ma>,
|
|
/* mac_rxd3 */
|
|
<3 RK_PA3 1 &pcfg_pull_none>,
|
|
/* mac_rxd2 */
|
|
<3 RK_PA2 1 &pcfg_pull_none>,
|
|
/* mac_txd3 */
|
|
<3 RK_PA1 1 &pcfg_pull_none_13ma>,
|
|
/* mac_txd2 */
|
|
<3 RK_PA0 1 &pcfg_pull_none_13ma>;
|
|
};
|
|
|
|
rmii_pins: rmii-pins {
|
|
rockchip,pins =
|
|
/* mac_mdio */
|
|
<3 RK_PB5 1 &pcfg_pull_none>,
|
|
/* mac_txen */
|
|
<3 RK_PB4 1 &pcfg_pull_none_13ma>,
|
|
/* mac_clk */
|
|
<3 RK_PB3 1 &pcfg_pull_none>,
|
|
/* mac_rxer */
|
|
<3 RK_PB2 1 &pcfg_pull_none>,
|
|
/* mac_rxdv */
|
|
<3 RK_PB1 1 &pcfg_pull_none>,
|
|
/* mac_mdc */
|
|
<3 RK_PB0 1 &pcfg_pull_none>,
|
|
/* mac_rxd1 */
|
|
<3 RK_PA7 1 &pcfg_pull_none>,
|
|
/* mac_rxd0 */
|
|
<3 RK_PA6 1 &pcfg_pull_none>,
|
|
/* mac_txd1 */
|
|
<3 RK_PA5 1 &pcfg_pull_none_13ma>,
|
|
/* mac_txd0 */
|
|
<3 RK_PA4 1 &pcfg_pull_none_13ma>;
|
|
};
|
|
};
|
|
|
|
i2c0 {
|
|
i2c0_xfer: i2c0-xfer {
|
|
rockchip,pins =
|
|
<1 RK_PB7 2 &pcfg_pull_none>,
|
|
<1 RK_PC0 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c1 {
|
|
i2c1_xfer: i2c1-xfer {
|
|
rockchip,pins =
|
|
<4 RK_PA2 1 &pcfg_pull_none>,
|
|
<4 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c2 {
|
|
i2c2_xfer: i2c2-xfer {
|
|
rockchip,pins =
|
|
<2 RK_PA1 2 &pcfg_pull_none_12ma>,
|
|
<2 RK_PA0 2 &pcfg_pull_none_12ma>;
|
|
};
|
|
};
|
|
|
|
i2c3 {
|
|
i2c3_xfer: i2c3-xfer {
|
|
rockchip,pins =
|
|
<4 RK_PC1 1 &pcfg_pull_none>,
|
|
<4 RK_PC0 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c4 {
|
|
i2c4_xfer: i2c4-xfer {
|
|
rockchip,pins =
|
|
<1 RK_PB4 1 &pcfg_pull_none>,
|
|
<1 RK_PB3 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c5 {
|
|
i2c5_xfer: i2c5-xfer {
|
|
rockchip,pins =
|
|
<3 RK_PB3 2 &pcfg_pull_none>,
|
|
<3 RK_PB2 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c6 {
|
|
i2c6_xfer: i2c6-xfer {
|
|
rockchip,pins =
|
|
<2 RK_PB2 2 &pcfg_pull_none>,
|
|
<2 RK_PB1 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c7 {
|
|
i2c7_xfer: i2c7-xfer {
|
|
rockchip,pins =
|
|
<2 RK_PB0 2 &pcfg_pull_none>,
|
|
<2 RK_PA7 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c8 {
|
|
i2c8_xfer: i2c8-xfer {
|
|
rockchip,pins =
|
|
<1 RK_PC5 1 &pcfg_pull_none>,
|
|
<1 RK_PC4 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2s0 {
|
|
i2s0_2ch_bus: i2s0-2ch-bus {
|
|
rockchip,pins =
|
|
<3 RK_PD0 1 &pcfg_pull_none>,
|
|
<3 RK_PD1 1 &pcfg_pull_none>,
|
|
<3 RK_PD2 1 &pcfg_pull_none>,
|
|
<3 RK_PD3 1 &pcfg_pull_none>,
|
|
<3 RK_PD7 1 &pcfg_pull_none>,
|
|
<4 RK_PA0 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s0_8ch_bus: i2s0-8ch-bus {
|
|
rockchip,pins =
|
|
<3 RK_PD0 1 &pcfg_pull_none>,
|
|
<3 RK_PD1 1 &pcfg_pull_none>,
|
|
<3 RK_PD2 1 &pcfg_pull_none>,
|
|
<3 RK_PD3 1 &pcfg_pull_none>,
|
|
<3 RK_PD4 1 &pcfg_pull_none>,
|
|
<3 RK_PD5 1 &pcfg_pull_none>,
|
|
<3 RK_PD6 1 &pcfg_pull_none>,
|
|
<3 RK_PD7 1 &pcfg_pull_none>,
|
|
<4 RK_PA0 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2s1 {
|
|
i2s1_2ch_bus: i2s1-2ch-bus {
|
|
rockchip,pins =
|
|
<4 RK_PA3 1 &pcfg_pull_none>,
|
|
<4 RK_PA4 1 &pcfg_pull_none>,
|
|
<4 RK_PA5 1 &pcfg_pull_none>,
|
|
<4 RK_PA6 1 &pcfg_pull_none>,
|
|
<4 RK_PA7 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sdio0 {
|
|
sdio0_bus1: sdio0-bus1 {
|
|
rockchip,pins =
|
|
<2 RK_PC4 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_bus4: sdio0-bus4 {
|
|
rockchip,pins =
|
|
<2 RK_PC4 1 &pcfg_pull_up>,
|
|
<2 RK_PC5 1 &pcfg_pull_up>,
|
|
<2 RK_PC6 1 &pcfg_pull_up>,
|
|
<2 RK_PC7 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_cmd: sdio0-cmd {
|
|
rockchip,pins =
|
|
<2 RK_PD0 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_clk: sdio0-clk {
|
|
rockchip,pins =
|
|
<2 RK_PD1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sdio0_cd: sdio0-cd {
|
|
rockchip,pins =
|
|
<2 RK_PD2 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_pwr: sdio0-pwr {
|
|
rockchip,pins =
|
|
<2 RK_PD3 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_bkpwr: sdio0-bkpwr {
|
|
rockchip,pins =
|
|
<2 RK_PD4 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_wp: sdio0-wp {
|
|
rockchip,pins =
|
|
<0 RK_PA3 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_int: sdio0-int {
|
|
rockchip,pins =
|
|
<0 RK_PA4 1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
sdmmc {
|
|
sdmmc_bus1: sdmmc-bus1 {
|
|
rockchip,pins =
|
|
<4 RK_PB0 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdmmc_bus4: sdmmc-bus4 {
|
|
rockchip,pins =
|
|
<4 RK_PB0 1 &pcfg_pull_up>,
|
|
<4 RK_PB1 1 &pcfg_pull_up>,
|
|
<4 RK_PB2 1 &pcfg_pull_up>,
|
|
<4 RK_PB3 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdmmc_clk: sdmmc-clk {
|
|
rockchip,pins =
|
|
<4 RK_PB4 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sdmmc_cmd: sdmmc-cmd {
|
|
rockchip,pins =
|
|
<4 RK_PB5 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdmmc_cd: sdmmc-cd {
|
|
rockchip,pins =
|
|
<0 RK_PA7 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdmmc_wp: sdmmc-wp {
|
|
rockchip,pins =
|
|
<0 RK_PB0 1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
sleep {
|
|
ap_pwroff: ap-pwroff {
|
|
rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
ddrio_pwroff: ddrio-pwroff {
|
|
rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spdif {
|
|
spdif_bus: spdif-bus {
|
|
rockchip,pins =
|
|
<4 RK_PC5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
spdif_bus_1: spdif-bus-1 {
|
|
rockchip,pins =
|
|
<3 RK_PC0 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spi0 {
|
|
spi0_clk: spi0-clk {
|
|
rockchip,pins =
|
|
<3 RK_PA6 2 &pcfg_pull_up>;
|
|
};
|
|
spi0_cs0: spi0-cs0 {
|
|
rockchip,pins =
|
|
<3 RK_PA7 2 &pcfg_pull_up>;
|
|
};
|
|
spi0_cs1: spi0-cs1 {
|
|
rockchip,pins =
|
|
<3 RK_PB0 2 &pcfg_pull_up>;
|
|
};
|
|
spi0_tx: spi0-tx {
|
|
rockchip,pins =
|
|
<3 RK_PA5 2 &pcfg_pull_up>;
|
|
};
|
|
spi0_rx: spi0-rx {
|
|
rockchip,pins =
|
|
<3 RK_PA4 2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi1 {
|
|
spi1_clk: spi1-clk {
|
|
rockchip,pins =
|
|
<1 RK_PB1 2 &pcfg_pull_up>;
|
|
};
|
|
spi1_cs0: spi1-cs0 {
|
|
rockchip,pins =
|
|
<1 RK_PB2 2 &pcfg_pull_up>;
|
|
};
|
|
spi1_rx: spi1-rx {
|
|
rockchip,pins =
|
|
<1 RK_PA7 2 &pcfg_pull_up>;
|
|
};
|
|
spi1_tx: spi1-tx {
|
|
rockchip,pins =
|
|
<1 RK_PB0 2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi2 {
|
|
spi2_clk: spi2-clk {
|
|
rockchip,pins =
|
|
<2 RK_PB3 1 &pcfg_pull_up>;
|
|
};
|
|
spi2_cs0: spi2-cs0 {
|
|
rockchip,pins =
|
|
<2 RK_PB4 1 &pcfg_pull_up>;
|
|
};
|
|
spi2_rx: spi2-rx {
|
|
rockchip,pins =
|
|
<2 RK_PB1 1 &pcfg_pull_up>;
|
|
};
|
|
spi2_tx: spi2-tx {
|
|
rockchip,pins =
|
|
<2 RK_PB2 1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi3 {
|
|
spi3_clk: spi3-clk {
|
|
rockchip,pins =
|
|
<1 RK_PC1 1 &pcfg_pull_up>;
|
|
};
|
|
spi3_cs0: spi3-cs0 {
|
|
rockchip,pins =
|
|
<1 RK_PC2 1 &pcfg_pull_up>;
|
|
};
|
|
spi3_rx: spi3-rx {
|
|
rockchip,pins =
|
|
<1 RK_PB7 1 &pcfg_pull_up>;
|
|
};
|
|
spi3_tx: spi3-tx {
|
|
rockchip,pins =
|
|
<1 RK_PC0 1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi4 {
|
|
spi4_clk: spi4-clk {
|
|
rockchip,pins =
|
|
<3 RK_PA2 2 &pcfg_pull_up>;
|
|
};
|
|
spi4_cs0: spi4-cs0 {
|
|
rockchip,pins =
|
|
<3 RK_PA3 2 &pcfg_pull_up>;
|
|
};
|
|
spi4_rx: spi4-rx {
|
|
rockchip,pins =
|
|
<3 RK_PA0 2 &pcfg_pull_up>;
|
|
};
|
|
spi4_tx: spi4-tx {
|
|
rockchip,pins =
|
|
<3 RK_PA1 2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi5 {
|
|
spi5_clk: spi5-clk {
|
|
rockchip,pins =
|
|
<2 RK_PC6 2 &pcfg_pull_up>;
|
|
};
|
|
spi5_cs0: spi5-cs0 {
|
|
rockchip,pins =
|
|
<2 RK_PC7 2 &pcfg_pull_up>;
|
|
};
|
|
spi5_rx: spi5-rx {
|
|
rockchip,pins =
|
|
<2 RK_PC4 2 &pcfg_pull_up>;
|
|
};
|
|
spi5_tx: spi5-tx {
|
|
rockchip,pins =
|
|
<2 RK_PC5 2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
testclk {
|
|
test_clkout0: test-clkout0 {
|
|
rockchip,pins =
|
|
<0 RK_PA0 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
test_clkout1: test-clkout1 {
|
|
rockchip,pins =
|
|
<2 RK_PD1 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
test_clkout2: test-clkout2 {
|
|
rockchip,pins =
|
|
<0 RK_PB0 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
tsadc {
|
|
otp_gpio: otp-gpio {
|
|
rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
|
|
otp_out: otp-out {
|
|
rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
uart0_xfer: uart0-xfer {
|
|
rockchip,pins =
|
|
<2 RK_PC0 1 &pcfg_pull_up>,
|
|
<2 RK_PC1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_cts: uart0-cts {
|
|
rockchip,pins =
|
|
<2 RK_PC2 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_rts: uart0-rts {
|
|
rockchip,pins =
|
|
<2 RK_PC3 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
uart1_xfer: uart1-xfer {
|
|
rockchip,pins =
|
|
<3 RK_PB4 2 &pcfg_pull_up>,
|
|
<3 RK_PB5 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2a {
|
|
uart2a_xfer: uart2a-xfer {
|
|
rockchip,pins =
|
|
<4 RK_PB0 2 &pcfg_pull_up>,
|
|
<4 RK_PB1 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2b {
|
|
uart2b_xfer: uart2b-xfer {
|
|
rockchip,pins =
|
|
<4 RK_PC0 2 &pcfg_pull_up>,
|
|
<4 RK_PC1 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2c {
|
|
uart2c_xfer: uart2c-xfer {
|
|
rockchip,pins =
|
|
<4 RK_PC3 1 &pcfg_pull_up>,
|
|
<4 RK_PC4 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart3 {
|
|
uart3_xfer: uart3-xfer {
|
|
rockchip,pins =
|
|
<3 RK_PB6 2 &pcfg_pull_up>,
|
|
<3 RK_PB7 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart3_cts: uart3-cts {
|
|
rockchip,pins =
|
|
<3 RK_PC0 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart3_rts: uart3-rts {
|
|
rockchip,pins =
|
|
<3 RK_PC1 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart4 {
|
|
uart4_xfer: uart4-xfer {
|
|
rockchip,pins =
|
|
<1 RK_PA7 1 &pcfg_pull_up>,
|
|
<1 RK_PB0 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uarthdcp {
|
|
uarthdcp_xfer: uarthdcp-xfer {
|
|
rockchip,pins =
|
|
<4 RK_PC5 2 &pcfg_pull_up>,
|
|
<4 RK_PC6 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm0 {
|
|
pwm0_pin: pwm0-pin {
|
|
rockchip,pins =
|
|
<4 RK_PC2 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm0_pin_pull_down: pwm0-pin-pull-down {
|
|
rockchip,pins =
|
|
<4 RK_PC2 1 &pcfg_pull_down>;
|
|
};
|
|
|
|
vop0_pwm_pin: vop0-pwm-pin {
|
|
rockchip,pins =
|
|
<4 RK_PC2 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
vop1_pwm_pin: vop1-pwm-pin {
|
|
rockchip,pins =
|
|
<4 RK_PC2 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm1 {
|
|
pwm1_pin: pwm1-pin {
|
|
rockchip,pins =
|
|
<4 RK_PC6 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm1_pin_pull_down: pwm1-pin-pull-down {
|
|
rockchip,pins =
|
|
<4 RK_PC6 1 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
pwm2 {
|
|
pwm2_pin: pwm2-pin {
|
|
rockchip,pins =
|
|
<1 RK_PC3 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm2_pin_pull_down: pwm2-pin-pull-down {
|
|
rockchip,pins =
|
|
<1 RK_PC3 1 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
pwm3a {
|
|
pwm3a_pin: pwm3a-pin {
|
|
rockchip,pins =
|
|
<0 RK_PA6 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm3b {
|
|
pwm3b_pin: pwm3b-pin {
|
|
rockchip,pins =
|
|
<1 RK_PB6 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
hdmi {
|
|
hdmi_i2c_xfer: hdmi-i2c-xfer {
|
|
rockchip,pins =
|
|
<4 RK_PC1 3 &pcfg_pull_none>,
|
|
<4 RK_PC0 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
hdmi_cec: hdmi-cec {
|
|
rockchip,pins =
|
|
<4 RK_PC7 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pcie {
|
|
pcie_clkreqn_cpm: pci-clkreqn-cpm {
|
|
rockchip,pins =
|
|
<2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
|
|
pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
|
|
rockchip,pins =
|
|
<4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|