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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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825637b9c0
DSI byte clock and pixel clocks are sourced from DSI PLL. This change adds the DSI PLL source clock driver under common clock framework. This change handles DSI 28nm PLL only. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Wentao Xu <wentaox@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
65 lines
1.4 KiB
Makefile
65 lines
1.4 KiB
Makefile
ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/msm
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ccflags-$(CONFIG_DRM_MSM_DSI_PLL) += -Idrivers/gpu/drm/msm/dsi
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msm-y := \
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adreno/adreno_device.o \
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adreno/adreno_gpu.o \
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adreno/a3xx_gpu.o \
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adreno/a4xx_gpu.o \
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hdmi/hdmi.o \
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hdmi/hdmi_audio.o \
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hdmi/hdmi_bridge.o \
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hdmi/hdmi_connector.o \
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hdmi/hdmi_i2c.o \
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hdmi/hdmi_phy_8960.o \
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hdmi/hdmi_phy_8x60.o \
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hdmi/hdmi_phy_8x74.o \
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edp/edp.o \
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edp/edp_aux.o \
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edp/edp_bridge.o \
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edp/edp_connector.o \
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edp/edp_ctrl.o \
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edp/edp_phy.o \
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mdp/mdp_format.o \
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mdp/mdp_kms.o \
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mdp/mdp4/mdp4_crtc.o \
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mdp/mdp4/mdp4_dtv_encoder.o \
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mdp/mdp4/mdp4_lcdc_encoder.o \
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mdp/mdp4/mdp4_lvds_connector.o \
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mdp/mdp4/mdp4_irq.o \
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mdp/mdp4/mdp4_kms.o \
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mdp/mdp4/mdp4_plane.o \
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mdp/mdp5/mdp5_cfg.o \
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mdp/mdp5/mdp5_ctl.o \
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mdp/mdp5/mdp5_crtc.o \
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mdp/mdp5/mdp5_encoder.o \
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mdp/mdp5/mdp5_irq.o \
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mdp/mdp5/mdp5_kms.o \
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mdp/mdp5/mdp5_plane.o \
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mdp/mdp5/mdp5_smp.o \
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msm_atomic.o \
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msm_drv.o \
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msm_fb.o \
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msm_gem.o \
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msm_gem_prime.o \
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msm_gem_submit.o \
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msm_gpu.o \
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msm_iommu.o \
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msm_perf.o \
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msm_rd.o \
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msm_ringbuffer.o
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msm-$(CONFIG_DRM_MSM_FBDEV) += msm_fbdev.o
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msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o
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msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
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dsi/dsi_host.o \
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dsi/dsi_manager.o \
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dsi/dsi_phy.o \
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mdp/mdp5/mdp5_cmd_encoder.o
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msm-$(CONFIG_DRM_MSM_DSI_PLL) += dsi/pll/dsi_pll.o \
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dsi/pll/dsi_pll_28nm.o
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obj-$(CONFIG_DRM_MSM) += msm.o
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