mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 08:08:09 +07:00
b0c28f2765
The OPP properties, like "operating-points", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can create an OPP table. Add such missing properties. Fix other missing property (clock latency) as well to make it all work. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
555 lines
15 KiB
Plaintext
555 lines
15 KiB
Plaintext
/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/dts-v1/;
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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model = "Qualcomm Technologies, Inc. IPQ4019";
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compatible = "qcom,ipq4019";
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interrupt-parent = <&intc>;
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reserved-memory {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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ranges;
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smem_region: smem@87e00000 {
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reg = <0x87e00000 0x080000>;
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no-map;
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};
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tz@87e80000 {
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reg = <0x87e80000 0x180000>;
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no-map;
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};
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};
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aliases {
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spi0 = &blsp1_spi1;
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spi1 = &blsp1_spi2;
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i2c0 = &blsp1_i2c3;
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i2c1 = &blsp1_i2c4;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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enable-method = "qcom,kpss-acc-v1";
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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reg = <0x0>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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operating-points = <
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/* kHz uV (fixed) */
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48000 1100000
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200000 1100000
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500000 1100000
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716000 1100000
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>;
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clock-latency = <256000>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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enable-method = "qcom,kpss-acc-v1";
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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reg = <0x1>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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operating-points = <
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/* kHz uV (fixed) */
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48000 1100000
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200000 1100000
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500000 1100000
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666000 1100000
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>;
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clock-latency = <256000>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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enable-method = "qcom,kpss-acc-v1";
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qcom,acc = <&acc2>;
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qcom,saw = <&saw2>;
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reg = <0x2>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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operating-points = <
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/* kHz uV (fixed) */
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48000 1100000
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200000 1100000
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500000 1100000
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666000 1100000
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>;
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clock-latency = <256000>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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enable-method = "qcom,kpss-acc-v1";
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qcom,acc = <&acc3>;
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qcom,saw = <&saw3>;
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reg = <0x3>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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operating-points = <
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/* kHz uV (fixed) */
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48000 1100000
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200000 1100000
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500000 1100000
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666000 1100000
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>;
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clock-latency = <256000>;
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};
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};
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pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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clocks {
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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xo: xo {
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compatible = "fixed-clock";
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clock-frequency = <48000000>;
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#clock-cells = <0>;
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-ipq4019";
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 2 0xf08>,
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<1 3 0xf08>,
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<1 4 0xf08>,
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<1 1 0xf08>;
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clock-frequency = <48000000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x0b000000 0x1000>,
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<0x0b002000 0x1000>;
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};
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gcc: clock-controller@1800000 {
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compatible = "qcom,gcc-ipq4019";
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#clock-cells = <1>;
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#reset-cells = <1>;
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reg = <0x1800000 0x60000>;
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};
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rng@22000 {
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compatible = "qcom,prng";
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reg = <0x22000 0x140>;
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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clock-names = "core";
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status = "disabled";
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};
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq4019-pinctrl";
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reg = <0x01000000 0x300000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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};
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blsp_dma: dma@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x07884000 0x23000>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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status = "disabled";
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};
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blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x78b5000 0x600>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&blsp_dma 5>, <&blsp_dma 4>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x78b6000 0x600>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&blsp_dma 7>, <&blsp_dma 6>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x78b7000 0x600>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&blsp_dma 9>, <&blsp_dma 8>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x78b8000 0x600>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&blsp_dma 11>, <&blsp_dma 10>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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cryptobam: dma@8e04000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x08e04000 0x20000>;
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interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <1>;
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qcom,controlled-remotely;
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status = "disabled";
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};
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crypto@8e3a000 {
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compatible = "qcom,crypto-v5.1";
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reg = <0x08e3a000 0x6000>;
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clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
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<&gcc GCC_CRYPTO_AXI_CLK>,
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<&gcc GCC_CRYPTO_CLK>;
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clock-names = "iface", "bus", "core";
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dmas = <&cryptobam 2>, <&cryptobam 3>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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acc0: clock-controller@b088000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
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};
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acc1: clock-controller@b098000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
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};
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acc2: clock-controller@b0a8000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
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};
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acc3: clock-controller@b0b8000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
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};
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saw0: regulator@b089000 {
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compatible = "qcom,saw2";
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reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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};
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saw1: regulator@b099000 {
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compatible = "qcom,saw2";
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reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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};
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saw2: regulator@b0a9000 {
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compatible = "qcom,saw2";
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reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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};
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saw3: regulator@b0b9000 {
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compatible = "qcom,saw2";
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reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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};
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blsp1_uart1: serial@78af000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78af000 0x200>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp_dma 1>, <&blsp_dma 0>;
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dma-names = "rx", "tx";
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};
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blsp1_uart2: serial@78b0000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78b0000 0x200>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp_dma 3>, <&blsp_dma 2>;
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dma-names = "rx", "tx";
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};
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watchdog@b017000 {
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compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
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reg = <0xb017000 0x40>;
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clocks = <&sleep_clk>;
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timeout-sec = <10>;
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status = "disabled";
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};
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restart@4ab000 {
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compatible = "qcom,pshold";
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reg = <0x4ab000 0x4>;
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};
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pcie0: pci@40000000 {
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compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
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reg = <0x40000000 0xf1d
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0x40000f20 0xa8
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0x80000 0x2000
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0x40100000 0x1000>;
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reg-names = "dbi", "elbi", "parf", "config";
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device_type = "pci";
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
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0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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clocks = <&gcc GCC_PCIE_AHB_CLK>,
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<&gcc GCC_PCIE_AXI_M_CLK>,
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<&gcc GCC_PCIE_AXI_S_CLK>;
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clock-names = "aux",
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"master_bus",
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"slave_bus";
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resets = <&gcc PCIE_AXI_M_ARES>,
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<&gcc PCIE_AXI_S_ARES>,
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<&gcc PCIE_PIPE_ARES>,
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<&gcc PCIE_AXI_M_VMIDMT_ARES>,
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<&gcc PCIE_AXI_S_XPU_ARES>,
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<&gcc PCIE_PARF_XPU_ARES>,
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<&gcc PCIE_PHY_ARES>,
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<&gcc PCIE_AXI_M_STICKY_ARES>,
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<&gcc PCIE_PIPE_STICKY_ARES>,
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<&gcc PCIE_PWR_ARES>,
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<&gcc PCIE_AHB_ARES>,
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<&gcc PCIE_PHY_AHB_ARES>;
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reset-names = "axi_m",
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"axi_s",
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"pipe",
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"axi_m_vmid",
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"axi_s_xpu",
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"parf",
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"phy",
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"axi_m_sticky",
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"pipe_sticky",
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"pwr",
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"ahb",
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"phy_ahb";
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status = "disabled";
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};
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qpic_bam: dma@7984000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x7984000 0x1a000>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QPIC_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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status = "disabled";
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};
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nand: qpic-nand@79b0000 {
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compatible = "qcom,ipq4019-nand";
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reg = <0x79b0000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcc GCC_QPIC_CLK>,
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<&gcc GCC_QPIC_AHB_CLK>;
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clock-names = "core", "aon";
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dmas = <&qpic_bam 0>,
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<&qpic_bam 1>,
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<&qpic_bam 2>;
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dma-names = "tx", "rx", "cmd";
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status = "disabled";
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nand@0 {
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reg = <0>;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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nand-bus-width = <8>;
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};
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};
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wifi0: wifi@a000000 {
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compatible = "qcom,ipq4019-wifi";
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reg = <0xa000000 0x200000>;
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resets = <&gcc WIFI0_CPU_INIT_RESET>,
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<&gcc WIFI0_RADIO_SRIF_RESET>,
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<&gcc WIFI0_RADIO_WARM_RESET>,
|
|
<&gcc WIFI0_RADIO_COLD_RESET>,
|
|
<&gcc WIFI0_CORE_WARM_RESET>,
|
|
<&gcc WIFI0_CORE_COLD_RESET>;
|
|
reset-names = "wifi_cpu_init", "wifi_radio_srif",
|
|
"wifi_radio_warm", "wifi_radio_cold",
|
|
"wifi_core_warm", "wifi_core_cold";
|
|
clocks = <&gcc GCC_WCSS2G_CLK>,
|
|
<&gcc GCC_WCSS2G_REF_CLK>,
|
|
<&gcc GCC_WCSS2G_RTC_CLK>;
|
|
clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
|
|
"wifi_wcss_rtc";
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
|
"msi4", "msi5", "msi6", "msi7",
|
|
"msi8", "msi9", "msi10", "msi11",
|
|
"msi12", "msi13", "msi14", "msi15",
|
|
"legacy";
|
|
status = "disabled";
|
|
};
|
|
|
|
wifi1: wifi@a800000 {
|
|
compatible = "qcom,ipq4019-wifi";
|
|
reg = <0xa800000 0x200000>;
|
|
resets = <&gcc WIFI1_CPU_INIT_RESET>,
|
|
<&gcc WIFI1_RADIO_SRIF_RESET>,
|
|
<&gcc WIFI1_RADIO_WARM_RESET>,
|
|
<&gcc WIFI1_RADIO_COLD_RESET>,
|
|
<&gcc WIFI1_CORE_WARM_RESET>,
|
|
<&gcc WIFI1_CORE_COLD_RESET>;
|
|
reset-names = "wifi_cpu_init", "wifi_radio_srif",
|
|
"wifi_radio_warm", "wifi_radio_cold",
|
|
"wifi_core_warm", "wifi_core_cold";
|
|
clocks = <&gcc GCC_WCSS5G_CLK>,
|
|
<&gcc GCC_WCSS5G_REF_CLK>,
|
|
<&gcc GCC_WCSS5G_RTC_CLK>;
|
|
clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
|
|
"wifi_wcss_rtc";
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
|
"msi4", "msi5", "msi6", "msi7",
|
|
"msi8", "msi9", "msi10", "msi11",
|
|
"msi12", "msi13", "msi14", "msi15",
|
|
"legacy";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|