mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 08:08:09 +07:00
0ae1177480
Use the new bindings of the Marvell NAND controller driver. Also adapt the NAND controller node organization to distinguish which property is relevant for the controller, and which one is NAND chip specific. Expose the partitions as a subnode of the NAND chip. Remove the 'marvell,nand-enable-arbiter' property, not needed anymore as the new driver activates the arbiter by default for all boards which is either needed or harmless. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
137 lines
2.1 KiB
Plaintext
137 lines
2.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
|
/*
|
|
* Device Tree file for Marvell Armada 395 GP board
|
|
*
|
|
* Copyright (C) 2016 Marvell
|
|
*
|
|
* Grzegorz Jaszczyk <jaz@semihalf.com>
|
|
*/
|
|
|
|
/dts-v1/;
|
|
#include "armada-395.dtsi"
|
|
|
|
/ {
|
|
model = "Marvell Armada 395 GP Board";
|
|
compatible = "marvell,a395-gp", "marvell,armada395",
|
|
"marvell,armada390";
|
|
|
|
chosen {
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
reg = <0x00000000 0x40000000>; /* 1 GB */
|
|
};
|
|
|
|
soc {
|
|
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
|
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
|
|
|
|
internal-regs {
|
|
i2c@11000 {
|
|
status = "okay";
|
|
clock-frequency = <100000>;
|
|
|
|
eeprom@57 {
|
|
compatible = "atmel,24c64";
|
|
reg = <0x57>;
|
|
};
|
|
};
|
|
|
|
serial@12000 {
|
|
/*
|
|
* Exported on the micro USB connector CON17
|
|
* through an FTDI
|
|
*/
|
|
status = "okay";
|
|
};
|
|
|
|
/* CON1 */
|
|
usb@58000 {
|
|
status = "okay";
|
|
};
|
|
|
|
/* CON2 */
|
|
sata@a8000 {
|
|
status = "okay";
|
|
};
|
|
|
|
/* CON18 */
|
|
sdhci@d8000 {
|
|
clock-frequency = <200000000>;
|
|
broken-cd;
|
|
wp-inverted;
|
|
bus-width = <8>;
|
|
status = "okay";
|
|
no-1-8-v;
|
|
};
|
|
|
|
/* CON4 */
|
|
usb3@f0000 {
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
pcie {
|
|
status = "okay";
|
|
|
|
/*
|
|
* The two PCIe units are accessible through
|
|
* mini PCIe slot on the board.
|
|
*/
|
|
|
|
/* CON7 */
|
|
pcie@2,0 {
|
|
/* Port 1, Lane 0 */
|
|
status = "okay";
|
|
};
|
|
|
|
/* CON8 */
|
|
pcie@4,0 {
|
|
/* Port 3, Lane 0 */
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&nand_controller {
|
|
status = "okay";
|
|
pinctrl-0 = <&nand_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
nand@0 {
|
|
reg = <0>;
|
|
label = "pxa3xx_nand-0";
|
|
nand-rb = <0>;
|
|
marvell,nand-keep-config;
|
|
nand-on-flash-bbt;
|
|
nand-ecc-strength = <4>;
|
|
nand-ecc-step-size = <512>;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "U-Boot";
|
|
reg = <0x00000000 0x00600000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@800000 {
|
|
label = "uImage";
|
|
reg = <0x00600000 0x00400000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@1000000 {
|
|
label = "Root";
|
|
reg = <0x00a00000 0x3f600000>;
|
|
};
|
|
};
|
|
};
|
|
};
|