mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 17:01:57 +07:00
0890a26479
ARCv2 is the next generation ISA from Synopsys and basis for the
HS3{4,6,8} families of processors which retain the traditional ARC mantra of
low power and configurability and are now more performant and feature rich.
HS38x is a 10 stage pipeline core which supports MMU (with huge pages) and
SMP (upto 4 cores) among other features.
+ www.synopsys.com/dw/ipdir.php?ds=arc-hs38-processor
+ http://news.synopsys.com/2014-10-14-New-DesignWare-ARC-HS38-Processor-Doubles-Performance-for-Embedded-Linux-Applications
+ http://www.embedded.com/electronics-news/4435975/Synopsys-ARC-HS38-core-gives-2X-boost-to-Linux-based-apps
- Support for ARC SDP (Software Development platform): Main Board + CPU Cards
= AXS101: CPU Card with ARC700 in silicon @ 700 MHz
= AXS103: CPU Card with HS38x in FPGA
- Refactoring of ARCompact port to accomodate new ARCv2 ISA
- Miscll updates/cleanups
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVk0g8AAoJEGnX8d3iisJecqsQAI6gvBC4GSNYDrmgGJJK1uLQ
uf6ZXQRLBtyxwa6VMvaNFe91i5XV5WvEXDuNBQX4FdYbp7Fs+Jz5VK79xFtbVEdU
H6mgKcs9HBwQvrHBxl54XxxXfX7kD1kxrlV7cL4b7bXTEX0XyH5ROUj600/YP+B4
8t+XdYcfgFK0HpeFGXVP+Xmv/e+hBbzCpOjOd2ZFqEwymvSpZDc4KZ2yDvV2+Ybn
JNZ421urQOrxR27njvvPvtpeN7uuJKfRYq7IuIR8+Ad72S19EDdw+DZHp2XoUMXA
wgydWrrOaX2Dr2CmXHGA1C4nWEG7+Yo9I1WitjJct0tkOQyDR2OIDGmvKGBd1uoS
QsihtoKBRvns+2gpXBEOmOHmF6ggpHNN0ppIwCp+AK5kX3fmxBtyUekyYmVpg8oQ
xgFIuJgmiAvW7QB7xIO6SFFt18De2ifDRrKWJwVauvfW/PvUIwuUBEcbh0OHAn54
ebUUWu2ZdVNe0XCsZOAQGwYHZRWBk8Bn3bhFpNnOliRiF77e9GsKeGYeIswYFy7I
42Gp35ftEj1pLLFZ1vIsAo72N6ErmHwPOcJkaBYaTbPGPcTEO2aR6b8WOcCjsPxK
DUeUV3H2HV+6V4jw/96lnsaRqsaj4TsJxEAFRR3wT1DLoRudCIDubaXTdvvDie77
RgKn4ZdxgmXD97+deBqc
=KwNo
-----END PGP SIGNATURE-----
Merge tag 'arc-4.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC architecture updates from Vineet Gupta:
- support for HS38 cores based on ARCv2 ISA
ARCv2 is the next generation ISA from Synopsys and basis for the
HS3{4,6,8} families of processors which retain the traditional ARC mantra of
low power and configurability and are now more performant and feature rich.
HS38x is a 10 stage pipeline core which supports MMU (with huge pages) and
SMP (upto 4 cores) among other features.
+ www.synopsys.com/dw/ipdir.php?ds=arc-hs38-processor
+ http://news.synopsys.com/2014-10-14-New-DesignWare-ARC-HS38-Processor-Doubles-Performance-for-Embedded-Linux-Applications
+ http://www.embedded.com/electronics-news/4435975/Synopsys-ARC-HS38-core-gives-2X-boost-to-Linux-based-apps
- support for ARC SDP (Software Development platform): Main Board + CPU Cards
= AXS101: CPU Card with ARC700 in silicon @ 700 MHz
= AXS103: CPU Card with HS38x in FPGA
- refactoring of ARCompact port to accomodate new ARCv2 ISA
- misc updates/cleanups
* tag 'arc-4.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (72 commits)
ARC: Fix build failures for ARCompact in linux-next after ARCv2 support
ARCv2: Allow older gcc to cope with new regime of ARCv2/ARCompact support
ARCv2: [vdk] dts files and defconfig for HS38 VDK
ARCv2: [axs103] Support ARC SDP FPGA platform for HS38x cores
ARC: [axs101] Prepare for AXS103
ARCv2: [nsim*hs*] Support simulation platforms for HS38x cores
ARCv2: All bits in place, allow ARCv2 builds
ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)
ARCv2: STAR 9000837815 workaround hardware exclusive transactions livelock
ARC: Reduce bitops lines of code using macros
ARCv2: barriers
arch: conditionally define smp_{mb,rmb,wmb}
ARC: add smp barriers around atomics per Documentation/atomic_ops.txt
ARC: add compiler barrier to LLSC based cmpxchg
ARCv2: SMP: intc: IDU 2nd level intc for dynamic IRQ distribution
ARCv2: SMP: clocksource: Enable Global Real Time counter
ARCv2: SMP: ARConnect debug/robustness
ARCv2: SMP: Support ARConnect (MCIP) for Inter-Core-Interrupts et al
ARC: make plat_smp_ops weak to allow over-rides
ARCv2: clocksource: Introduce 64bit local RTC counter
...
124 lines
2.4 KiB
C
124 lines
2.4 KiB
C
/*
|
|
* Generic barrier definitions, originally based on MN10300 definitions.
|
|
*
|
|
* It should be possible to use these on really simple architectures,
|
|
* but it serves more as a starting point for new ports.
|
|
*
|
|
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
|
|
* Written by David Howells (dhowells@redhat.com)
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public Licence
|
|
* as published by the Free Software Foundation; either version
|
|
* 2 of the Licence, or (at your option) any later version.
|
|
*/
|
|
#ifndef __ASM_GENERIC_BARRIER_H
|
|
#define __ASM_GENERIC_BARRIER_H
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
#include <linux/compiler.h>
|
|
|
|
#ifndef nop
|
|
#define nop() asm volatile ("nop")
|
|
#endif
|
|
|
|
/*
|
|
* Force strict CPU ordering. And yes, this is required on UP too when we're
|
|
* talking to devices.
|
|
*
|
|
* Fall back to compiler barriers if nothing better is provided.
|
|
*/
|
|
|
|
#ifndef mb
|
|
#define mb() barrier()
|
|
#endif
|
|
|
|
#ifndef rmb
|
|
#define rmb() mb()
|
|
#endif
|
|
|
|
#ifndef wmb
|
|
#define wmb() mb()
|
|
#endif
|
|
|
|
#ifndef dma_rmb
|
|
#define dma_rmb() rmb()
|
|
#endif
|
|
|
|
#ifndef dma_wmb
|
|
#define dma_wmb() wmb()
|
|
#endif
|
|
|
|
#ifndef read_barrier_depends
|
|
#define read_barrier_depends() do { } while (0)
|
|
#endif
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
#ifndef smp_mb
|
|
#define smp_mb() mb()
|
|
#endif
|
|
|
|
#ifndef smp_rmb
|
|
#define smp_rmb() rmb()
|
|
#endif
|
|
|
|
#ifndef smp_wmb
|
|
#define smp_wmb() wmb()
|
|
#endif
|
|
|
|
#ifndef smp_read_barrier_depends
|
|
#define smp_read_barrier_depends() read_barrier_depends()
|
|
#endif
|
|
|
|
#else /* !CONFIG_SMP */
|
|
|
|
#ifndef smp_mb
|
|
#define smp_mb() barrier()
|
|
#endif
|
|
|
|
#ifndef smp_rmb
|
|
#define smp_rmb() barrier()
|
|
#endif
|
|
|
|
#ifndef smp_wmb
|
|
#define smp_wmb() barrier()
|
|
#endif
|
|
|
|
#ifndef smp_read_barrier_depends
|
|
#define smp_read_barrier_depends() do { } while (0)
|
|
#endif
|
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
#ifndef smp_store_mb
|
|
#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0)
|
|
#endif
|
|
|
|
#ifndef smp_mb__before_atomic
|
|
#define smp_mb__before_atomic() smp_mb()
|
|
#endif
|
|
|
|
#ifndef smp_mb__after_atomic
|
|
#define smp_mb__after_atomic() smp_mb()
|
|
#endif
|
|
|
|
#define smp_store_release(p, v) \
|
|
do { \
|
|
compiletime_assert_atomic_type(*p); \
|
|
smp_mb(); \
|
|
ACCESS_ONCE(*p) = (v); \
|
|
} while (0)
|
|
|
|
#define smp_load_acquire(p) \
|
|
({ \
|
|
typeof(*p) ___p1 = ACCESS_ONCE(*p); \
|
|
compiletime_assert_atomic_type(*p); \
|
|
smp_mb(); \
|
|
___p1; \
|
|
})
|
|
|
|
#endif /* !__ASSEMBLY__ */
|
|
#endif /* __ASM_GENERIC_BARRIER_H */
|