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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ee38d94a0a
ARM64 randdconfig builds regularly run into a build error, especially
when NUMA_BALANCING and SPARSEMEM are enabled but not SPARSEMEM_VMEMMAP:
#error "KASAN: not enough bits in page flags for tag"
The last-cpuid bits are already contitional on the available space, so
the result of the calculation is a bit random on whether they were
already left out or not.
Adding the kasan tag bits before last-cpuid makes it much more likely to
end up with a successful build here, and should be reliable for
randconfig at least, as long as that does not randomize NR_CPUS or
NODES_SHIFT but uses the defaults.
In order for the modified check to not trigger in the x86 vdso32 code
where all constants are wrong (building with -m32), enclose all the
definitions with an #ifdef.
[arnd@arndb.de: build fix]
Link: http://lkml.kernel.org/r/CAK8P3a3Mno1SWTcuAOT0Wa9VS15pdU6EfnkxLbDpyS55yO04+g@mail.gmail.com
Link: http://lkml.kernel.org/r/20190722115520.3743282-1-arnd@arndb.de
Link: https://lore.kernel.org/lkml/20190618095347.3850490-1-arnd@arndb.de/
Fixes: 2813b9c029 ("kasan, mm, arm64: tag non slab memory allocated via pagealloc")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Andrey Konovalov <andreyknvl@google.com>
Reviewed-by: Andrey Ryabinin <aryabinin@virtuozzo.com>
Cc: Andrey Konovalov <andreyknvl@google.com>
Cc: Dmitry Vyukov <dvyukov@google.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Christoph Lameter <cl@linux.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
87 lines
2.0 KiB
C
87 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2015 Imagination Technologies
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* Author: Alex Smith <alex.smith@imgtec.com>
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*/
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#include <asm/sgidefs.h>
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#if _MIPS_SIM != _MIPS_SIM_ABI64 && defined(CONFIG_64BIT)
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/* Building 32-bit VDSO for the 64-bit kernel. Fake a 32-bit Kconfig. */
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#define BUILD_VDSO32_64
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#undef CONFIG_64BIT
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#define CONFIG_32BIT 1
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#ifndef __ASSEMBLY__
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#include <asm-generic/atomic64.h>
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#endif
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#endif
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#ifndef __ASSEMBLY__
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#include <asm/asm.h>
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#include <asm/page.h>
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#include <asm/vdso.h>
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static inline unsigned long get_vdso_base(void)
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{
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unsigned long addr;
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/*
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* We can't use cpu_has_mips_r6 since it needs the cpu_data[]
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* kernel symbol.
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*/
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#ifdef CONFIG_CPU_MIPSR6
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/*
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* lapc <symbol> is an alias to addiupc reg, <symbol> - .
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*
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* We can't use addiupc because there is no label-label
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* support for the addiupc reloc
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*/
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__asm__("lapc %0, _start \n"
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: "=r" (addr) : :);
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#else
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/*
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* Get the base load address of the VDSO. We have to avoid generating
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* relocations and references to the GOT because ld.so does not peform
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* relocations on the VDSO. We use the current offset from the VDSO base
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* and perform a PC-relative branch which gives the absolute address in
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* ra, and take the difference. The assembler chokes on
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* "li %0, _start - .", so embed the offset as a word and branch over
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* it.
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*
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*/
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__asm__(
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" .set push \n"
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" .set noreorder \n"
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" bal 1f \n"
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" nop \n"
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" .word _start - . \n"
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"1: lw %0, 0($31) \n"
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" " STR(PTR_ADDU) " %0, $31, %0 \n"
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" .set pop \n"
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: "=r" (addr)
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:
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: "$31");
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#endif /* CONFIG_CPU_MIPSR6 */
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return addr;
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}
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static inline const union mips_vdso_data *get_vdso_data(void)
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{
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return (const union mips_vdso_data *)(get_vdso_base() - PAGE_SIZE);
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}
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#ifdef CONFIG_CLKSRC_MIPS_GIC
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static inline void __iomem *get_gic(const union mips_vdso_data *data)
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{
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return (void __iomem *)data - PAGE_SIZE;
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}
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#endif /* CONFIG_CLKSRC_MIPS_GIC */
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#endif /* __ASSEMBLY__ */
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