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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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9d35dc3006
Current C-SKY ASID mechanism is from mips and it doesn't work well with multi-cores. ASID per core mechanism is not suitable for C-SKY SMP tlb maintain operations, eg: tlbi.vas need share the same asid in all processors and it'll invalid the tlb entry in all cores with the same asid. This patch is prepare for new ASID mechanism. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Arnd Bergmann <arnd@arndb.de>
310 lines
8.3 KiB
C
310 lines
8.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#ifndef __ASM_CSKY_PGTABLE_H
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#define __ASM_CSKY_PGTABLE_H
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#include <asm/fixmap.h>
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#include <asm/addrspace.h>
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#include <abi/pgtable-bits.h>
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#include <asm-generic/pgtable-nopmd.h>
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#define PGDIR_SHIFT 22
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
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#define FIRST_USER_ADDRESS 0UL
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#define PKMAP_BASE (0xff800000)
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#define VMALLOC_START (0xc0008000)
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#define VMALLOC_END (PKMAP_BASE - 2*PAGE_SIZE)
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/*
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* C-SKY is two-level paging structure:
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*/
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#define PGD_ORDER 0
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#define PTE_ORDER 0
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#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
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#define PTRS_PER_PMD 1
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#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
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#define pte_ERROR(e) \
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pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, (e).pte_low)
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#define pgd_ERROR(e) \
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pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
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/* Find an entry in the third-level page table.. */
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#define __pte_offset_t(address) \
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(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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#define pte_offset_kernel(dir, address) \
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(pmd_page_vaddr(*(dir)) + __pte_offset_t(address))
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#define pte_offset_map(dir, address) \
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((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset_t(address))
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#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
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#define pte_clear(mm, addr, ptep) set_pte((ptep), \
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(((unsigned int) addr & PAGE_OFFSET) ? __pte(_PAGE_GLOBAL) : __pte(0)))
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#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL))
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#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
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#define pte_pfn(x) ((unsigned long)((x).pte_low >> PAGE_SHIFT))
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#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) \
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| pgprot_val(prot))
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#define __READABLE (_PAGE_READ | _PAGE_VALID | _PAGE_ACCESSED)
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#define __WRITEABLE (_PAGE_WRITE | _PAGE_DIRTY | _PAGE_MODIFIED)
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#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | \
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_CACHE_MASK)
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#define pte_unmap(pte) ((void)(pte))
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#define __swp_type(x) (((x).val >> 4) & 0xff)
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#define __swp_offset(x) ((x).val >> 12)
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#define __swp_entry(type, offset) ((swp_entry_t) {((type) << 4) | \
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((offset) << 12) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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#define __mk_pte(page_nr, pgprot) __pte(((page_nr) << PAGE_SHIFT) | \
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pgprot_val(pgprot))
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/*
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* CSKY can't do page protection for execute, and considers that the same like
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* read. Also, write permissions imply read permissions. This is the closest
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* we can get by reasonable means..
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*/
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#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHED)
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#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
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_CACHE_CACHED)
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#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | _CACHE_CACHED)
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#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | _CACHE_CACHED)
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#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
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_PAGE_GLOBAL | _CACHE_CACHED)
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#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
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_CACHE_CACHED)
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#define __P000 PAGE_NONE
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#define __P001 PAGE_READONLY
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#define __P010 PAGE_COPY
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#define __P011 PAGE_COPY
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#define __P100 PAGE_READONLY
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#define __P101 PAGE_READONLY
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#define __P110 PAGE_COPY
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#define __P111 PAGE_COPY
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#define __S000 PAGE_NONE
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#define __S001 PAGE_READONLY
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#define __S010 PAGE_SHARED
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#define __S011 PAGE_SHARED
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#define __S100 PAGE_READONLY
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#define __S101 PAGE_READONLY
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#define __S110 PAGE_SHARED
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#define __S111 PAGE_SHARED
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extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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extern void load_pgd(unsigned long pg_dir);
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extern pte_t invalid_pte_table[PTRS_PER_PTE];
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static inline int pte_special(pte_t pte) { return 0; }
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static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
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static inline void set_pte(pte_t *p, pte_t pte)
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{
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*p = pte;
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#if defined(CONFIG_CPU_NEED_TLBSYNC)
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dcache_wb_line((u32)p);
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#endif
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/* prevent out of order excution */
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smp_mb();
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}
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#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
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static inline pte_t *pmd_page_vaddr(pmd_t pmd)
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{
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unsigned long ptr;
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ptr = pmd_val(pmd);
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return __va(ptr);
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}
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#define pmd_phys(pmd) pmd_val(pmd)
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static inline void set_pmd(pmd_t *p, pmd_t pmd)
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{
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*p = pmd;
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#if defined(CONFIG_CPU_NEED_TLBSYNC)
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dcache_wb_line((u32)p);
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#endif
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/* prevent specul excute */
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smp_mb();
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}
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static inline int pmd_none(pmd_t pmd)
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{
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return pmd_val(pmd) == __pa(invalid_pte_table);
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}
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#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
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static inline int pmd_present(pmd_t pmd)
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{
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return (pmd_val(pmd) != __pa(invalid_pte_table));
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}
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static inline void pmd_clear(pmd_t *p)
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{
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pmd_val(*p) = (__pa(invalid_pte_table));
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#if defined(CONFIG_CPU_NEED_TLBSYNC)
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dcache_wb_line((u32)p);
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#endif
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}
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/*
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* The following only work if pte_present() is true.
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* Undefined behaviour if not..
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*/
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static inline int pte_read(pte_t pte)
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{
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return pte.pte_low & _PAGE_READ;
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}
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static inline int pte_write(pte_t pte)
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{
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return (pte).pte_low & _PAGE_WRITE;
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}
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static inline int pte_dirty(pte_t pte)
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{
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return (pte).pte_low & _PAGE_MODIFIED;
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}
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static inline int pte_young(pte_t pte)
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{
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return (pte).pte_low & _PAGE_ACCESSED;
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}
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static inline pte_t pte_wrprotect(pte_t pte)
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{
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pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_DIRTY);
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return pte;
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}
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static inline pte_t pte_mkclean(pte_t pte)
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{
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pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_DIRTY);
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return pte;
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}
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static inline pte_t pte_mkold(pte_t pte)
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{
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pte_val(pte) &= ~(_PAGE_ACCESSED|_PAGE_VALID);
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return pte;
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}
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static inline pte_t pte_mkwrite(pte_t pte)
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{
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pte_val(pte) |= _PAGE_WRITE;
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if (pte_val(pte) & _PAGE_MODIFIED)
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pte_val(pte) |= _PAGE_DIRTY;
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return pte;
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}
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static inline pte_t pte_mkdirty(pte_t pte)
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{
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pte_val(pte) |= _PAGE_MODIFIED;
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if (pte_val(pte) & _PAGE_WRITE)
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pte_val(pte) |= _PAGE_DIRTY;
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return pte;
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}
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static inline pte_t pte_mkyoung(pte_t pte)
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{
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pte_val(pte) |= _PAGE_ACCESSED;
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if (pte_val(pte) & _PAGE_READ)
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pte_val(pte) |= _PAGE_VALID;
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return pte;
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}
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#define __pgd_offset(address) pgd_index(address)
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#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
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#define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
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/* to find an entry in a kernel page-table-directory */
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#define pgd_offset_k(address) pgd_offset(&init_mm, address)
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#define pgd_index(address) ((address) >> PGDIR_SHIFT)
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#define __HAVE_PHYS_MEM_ACCESS_PROT
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struct file;
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extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
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unsigned long size, pgprot_t vma_prot);
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/*
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* Macro to make mark a page protection value as "uncacheable". Note
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* that "protection" is really a misnomer here as the protection value
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* contains the memory attribute bits, dirty bits, and various other
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* bits as well.
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*/
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#define pgprot_noncached pgprot_noncached
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static inline pgprot_t pgprot_noncached(pgprot_t _prot)
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{
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unsigned long prot = pgprot_val(_prot);
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prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
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return __pgprot(prot);
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}
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/*
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* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*/
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#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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return __pte((pte_val(pte) & _PAGE_CHG_MASK) |
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(pgprot_val(newprot)));
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}
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/* to find an entry in a page-table-directory */
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static inline pgd_t *pgd_offset(struct mm_struct *mm, unsigned long address)
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{
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return mm->pgd + pgd_index(address);
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}
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/* Find an entry in the third-level page table.. */
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static inline pte_t *pte_offset(pmd_t *dir, unsigned long address)
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{
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return (pte_t *) (pmd_page_vaddr(*dir)) +
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((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
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}
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extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
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extern void paging_init(void);
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void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
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pte_t *pte);
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/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
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#define kern_addr_valid(addr) (1)
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/*
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* No page table caches to initialise
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*/
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#define pgtable_cache_init() do {} while (0)
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#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
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remap_pfn_range(vma, vaddr, pfn, size, prot)
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#include <asm-generic/pgtable.h>
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#endif /* __ASM_CSKY_PGTABLE_H */
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