mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-17 12:36:51 +07:00
2923f5ea77
This patch includes the exception/interrupt entries, pt_reg structure and
related accessors.
/* Unaligned accessing handling*/
Andes processors cannot load/store information which is not naturally
aligned on the bus, i.e., loading a 4 byte data whose start address must
be divisible by 4. If unaligned data accessing is happened, data
unaligned exception will be triggered and user will get SIGSEGV or
kernel oops according to the unaligned address. In order to make user be
able to load/store data from an unaligned address, software load/store
emulation is implemented in arch/nds32/mm/alignment.c to address data
unaligned exception.
Unaligned accessing handling is disabled by default because it is not a
normal case. User can enable this feature by following steps.
A. Compile time:
1. Enable kernel config CONFIG_ALIGNMENT_TRAP
B. Run time:
1. Enter /proc/sys/nds32/unaligned_acess folder
2. Write 1 to file enable_mode to enable unaligned accessing
handling. User can disable it by writing 0 to this file.
3. Write 1 to file debug to show which unaligned address is under
processing. User can disable it by writing 0 to this file.
However, unaligned accessing handler cannot work if this unaligned
address is not accessible such as protection violation. On this
condition, the default behaviors for addressing data unaligned exception
still happen
Signed-off-by: Vincent Chen <vincentc@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
577 lines
11 KiB
C
577 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2005-2017 Andes Technology Corporation
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#include <linux/proc_fs.h>
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#include <linux/uaccess.h>
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#include <linux/sysctl.h>
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#include <asm/unaligned.h>
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#define DEBUG(enable, tagged, ...) \
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do{ \
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if (enable) { \
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if (tagged) \
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pr_warn("[ %30s() ] ", __func__); \
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pr_warn(__VA_ARGS__); \
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} \
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} while (0)
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#define RT(inst) (((inst) >> 20) & 0x1FUL)
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#define RA(inst) (((inst) >> 15) & 0x1FUL)
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#define RB(inst) (((inst) >> 10) & 0x1FUL)
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#define SV(inst) (((inst) >> 8) & 0x3UL)
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#define IMM(inst) (((inst) >> 0) & 0x3FFFUL)
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#define RA3(inst) (((inst) >> 3) & 0x7UL)
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#define RT3(inst) (((inst) >> 6) & 0x7UL)
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#define IMM3U(inst) (((inst) >> 0) & 0x7UL)
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#define RA5(inst) (((inst) >> 0) & 0x1FUL)
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#define RT4(inst) (((inst) >> 5) & 0xFUL)
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#define __get8_data(val,addr,err) \
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__asm__( \
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"1: lbi.bi %1, [%2], #1\n" \
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"2:\n" \
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" .pushsection .text.fixup,\"ax\"\n" \
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" .align 2\n" \
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"3: movi %0, #1\n" \
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" j 2b\n" \
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" .popsection\n" \
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" .pushsection __ex_table,\"a\"\n" \
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" .align 3\n" \
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" .long 1b, 3b\n" \
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" .popsection\n" \
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: "=r" (err), "=&r" (val), "=r" (addr) \
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: "0" (err), "2" (addr))
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#define get16_data(addr, val_ptr) \
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do { \
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unsigned int err = 0, v, a = addr; \
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__get8_data(v,a,err); \
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*val_ptr = v << 0; \
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__get8_data(v,a,err); \
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*val_ptr |= v << 8; \
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if (err) \
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goto fault; \
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*val_ptr = le16_to_cpu(*val_ptr); \
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} while(0)
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#define get32_data(addr, val_ptr) \
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do { \
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unsigned int err = 0, v, a = addr; \
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__get8_data(v,a,err); \
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*val_ptr = v << 0; \
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__get8_data(v,a,err); \
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*val_ptr |= v << 8; \
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__get8_data(v,a,err); \
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*val_ptr |= v << 16; \
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__get8_data(v,a,err); \
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*val_ptr |= v << 24; \
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if (err) \
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goto fault; \
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*val_ptr = le32_to_cpu(*val_ptr); \
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} while(0)
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#define get_data(addr, val_ptr, len) \
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if (len == 2) \
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get16_data(addr, val_ptr); \
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else \
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get32_data(addr, val_ptr);
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#define set16_data(addr, val) \
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do { \
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unsigned int err = 0, *ptr = addr ; \
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val = le32_to_cpu(val); \
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__asm__( \
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"1: sbi.bi %2, [%1], #1\n" \
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" srli %2, %2, #8\n" \
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"2: sbi %2, [%1]\n" \
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"3:\n" \
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" .pushsection .text.fixup,\"ax\"\n" \
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" .align 2\n" \
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"4: movi %0, #1\n" \
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" j 3b\n" \
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" .popsection\n" \
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" .pushsection __ex_table,\"a\"\n" \
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" .align 3\n" \
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" .long 1b, 4b\n" \
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" .long 2b, 4b\n" \
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" .popsection\n" \
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: "=r" (err), "+r" (ptr), "+r" (val) \
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: "0" (err) \
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); \
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if (err) \
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goto fault; \
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} while(0)
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#define set32_data(addr, val) \
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do { \
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unsigned int err = 0, *ptr = addr ; \
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val = le32_to_cpu(val); \
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__asm__( \
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"1: sbi.bi %2, [%1], #1\n" \
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" srli %2, %2, #8\n" \
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"2: sbi.bi %2, [%1], #1\n" \
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" srli %2, %2, #8\n" \
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"3: sbi.bi %2, [%1], #1\n" \
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" srli %2, %2, #8\n" \
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"4: sbi %2, [%1]\n" \
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"5:\n" \
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" .pushsection .text.fixup,\"ax\"\n" \
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" .align 2\n" \
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"6: movi %0, #1\n" \
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" j 5b\n" \
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" .popsection\n" \
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" .pushsection __ex_table,\"a\"\n" \
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" .align 3\n" \
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" .long 1b, 6b\n" \
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" .long 2b, 6b\n" \
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" .long 3b, 6b\n" \
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" .long 4b, 6b\n" \
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" .popsection\n" \
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: "=r" (err), "+r" (ptr), "+r" (val) \
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: "0" (err) \
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); \
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if (err) \
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goto fault; \
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} while(0)
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#define set_data(addr, val, len) \
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if (len == 2) \
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set16_data(addr, val); \
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else \
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set32_data(addr, val);
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#define NDS32_16BIT_INSTRUCTION 0x80000000
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extern pte_t va_present(struct mm_struct *mm, unsigned long addr);
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extern pte_t va_kernel_present(unsigned long addr);
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extern int va_readable(struct pt_regs *regs, unsigned long addr);
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extern int va_writable(struct pt_regs *regs, unsigned long addr);
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int unalign_access_mode = 0, unalign_access_debug = 0;
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static inline unsigned long *idx_to_addr(struct pt_regs *regs, int idx)
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{
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/* this should be consistent with ptrace.h */
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if (idx >= 0 && idx <= 25) /* R0-R25 */
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return ®s->uregs[0] + idx;
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else if (idx >= 28 && idx <= 30) /* FP, GP, LP */
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return ®s->fp + (idx - 28);
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else if (idx == 31) /* SP */
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return ®s->sp;
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else
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return NULL; /* cause a segfault */
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}
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static inline unsigned long get_inst(unsigned long addr)
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{
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return be32_to_cpu(get_unaligned((u32 *) addr));
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}
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static inline unsigned long sign_extend(unsigned long val, int len)
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{
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unsigned long ret = 0;
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unsigned char *s, *t;
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int i = 0;
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val = cpu_to_le32(val);
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s = (void *)&val;
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t = (void *)&ret;
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while (i++ < len)
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*t++ = *s++;
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if (((*(t - 1)) & 0x80) && (i < 4)) {
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while (i++ <= 4)
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*t++ = 0xff;
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}
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return le32_to_cpu(ret);
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}
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static inline int do_16(unsigned long inst, struct pt_regs *regs)
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{
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int imm, regular, load, len, addr_mode, idx_mode;
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unsigned long unaligned_addr, target_val, source_idx, target_idx,
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shift = 0;
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switch ((inst >> 9) & 0x3F) {
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case 0x12: /* LHI333 */
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imm = 1;
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regular = 1;
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load = 1;
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len = 2;
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addr_mode = 3;
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idx_mode = 3;
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break;
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case 0x10: /* LWI333 */
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imm = 1;
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regular = 1;
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load = 1;
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len = 4;
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addr_mode = 3;
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idx_mode = 3;
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break;
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case 0x11: /* LWI333.bi */
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imm = 1;
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regular = 0;
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load = 1;
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len = 4;
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addr_mode = 3;
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idx_mode = 3;
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break;
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case 0x1A: /* LWI450 */
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imm = 0;
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regular = 1;
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load = 1;
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len = 4;
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addr_mode = 5;
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idx_mode = 4;
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break;
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case 0x16: /* SHI333 */
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imm = 1;
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regular = 1;
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load = 0;
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len = 2;
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addr_mode = 3;
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idx_mode = 3;
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break;
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case 0x14: /* SWI333 */
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imm = 1;
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regular = 1;
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load = 0;
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len = 4;
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addr_mode = 3;
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idx_mode = 3;
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break;
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case 0x15: /* SWI333.bi */
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imm = 1;
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regular = 0;
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load = 0;
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len = 4;
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addr_mode = 3;
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idx_mode = 3;
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break;
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case 0x1B: /* SWI450 */
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imm = 0;
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regular = 1;
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load = 0;
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len = 4;
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addr_mode = 5;
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idx_mode = 4;
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break;
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default:
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return -EFAULT;
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}
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if (addr_mode == 3) {
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unaligned_addr = *idx_to_addr(regs, RA3(inst));
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source_idx = RA3(inst);
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} else {
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unaligned_addr = *idx_to_addr(regs, RA5(inst));
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source_idx = RA5(inst);
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}
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if (idx_mode == 3)
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target_idx = RT3(inst);
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else
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target_idx = RT4(inst);
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if (imm)
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shift = IMM3U(inst) * len;
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if (regular)
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unaligned_addr += shift;
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if (load) {
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if (!access_ok(VERIFY_READ, (void *)unaligned_addr, len))
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return -EACCES;
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get_data(unaligned_addr, &target_val, len);
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*idx_to_addr(regs, target_idx) = target_val;
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} else {
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if (!access_ok(VERIFY_WRITE, (void *)unaligned_addr, len))
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return -EACCES;
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target_val = *idx_to_addr(regs, target_idx);
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set_data((void *)unaligned_addr, target_val, len);
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}
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if (!regular)
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*idx_to_addr(regs, source_idx) = unaligned_addr + shift;
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regs->ipc += 2;
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return 0;
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fault:
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return -EACCES;
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}
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static inline int do_32(unsigned long inst, struct pt_regs *regs)
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{
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int imm, regular, load, len, sign_ext;
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unsigned long unaligned_addr, target_val, shift;
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unaligned_addr = *idx_to_addr(regs, RA(inst));
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switch ((inst >> 25) << 1) {
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case 0x02: /* LHI */
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imm = 1;
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regular = 1;
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load = 1;
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len = 2;
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sign_ext = 0;
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break;
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case 0x0A: /* LHI.bi */
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imm = 1;
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regular = 0;
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load = 1;
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len = 2;
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sign_ext = 0;
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break;
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case 0x22: /* LHSI */
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imm = 1;
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regular = 1;
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load = 1;
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len = 2;
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sign_ext = 1;
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break;
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case 0x2A: /* LHSI.bi */
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imm = 1;
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regular = 0;
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load = 1;
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len = 2;
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sign_ext = 1;
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break;
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case 0x04: /* LWI */
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imm = 1;
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regular = 1;
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load = 1;
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len = 4;
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sign_ext = 0;
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break;
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case 0x0C: /* LWI.bi */
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imm = 1;
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regular = 0;
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load = 1;
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len = 4;
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sign_ext = 0;
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break;
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case 0x12: /* SHI */
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imm = 1;
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regular = 1;
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load = 0;
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len = 2;
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sign_ext = 0;
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break;
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case 0x1A: /* SHI.bi */
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imm = 1;
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regular = 0;
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load = 0;
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len = 2;
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sign_ext = 0;
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break;
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case 0x14: /* SWI */
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imm = 1;
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regular = 1;
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load = 0;
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len = 4;
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sign_ext = 0;
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break;
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case 0x1C: /* SWI.bi */
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imm = 1;
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regular = 0;
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load = 0;
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len = 4;
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sign_ext = 0;
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break;
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default:
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switch (inst & 0xff) {
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case 0x01: /* LH */
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imm = 0;
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regular = 1;
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load = 1;
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len = 2;
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sign_ext = 0;
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break;
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case 0x05: /* LH.bi */
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imm = 0;
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regular = 0;
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load = 1;
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len = 2;
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sign_ext = 0;
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break;
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case 0x11: /* LHS */
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imm = 0;
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regular = 1;
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load = 1;
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len = 2;
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sign_ext = 1;
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break;
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case 0x15: /* LHS.bi */
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imm = 0;
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regular = 0;
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load = 1;
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len = 2;
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sign_ext = 1;
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break;
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case 0x02: /* LW */
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imm = 0;
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regular = 1;
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load = 1;
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len = 4;
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sign_ext = 0;
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break;
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case 0x06: /* LW.bi */
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imm = 0;
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regular = 0;
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load = 1;
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len = 4;
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sign_ext = 0;
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break;
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case 0x09: /* SH */
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imm = 0;
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regular = 1;
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load = 0;
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len = 2;
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sign_ext = 0;
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break;
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case 0x0D: /* SH.bi */
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imm = 0;
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regular = 0;
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load = 0;
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len = 2;
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sign_ext = 0;
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break;
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case 0x0A: /* SW */
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imm = 0;
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regular = 1;
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load = 0;
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len = 4;
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sign_ext = 0;
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break;
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case 0x0E: /* SW.bi */
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imm = 0;
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regular = 0;
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load = 0;
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len = 4;
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sign_ext = 0;
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break;
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default:
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return -EFAULT;
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}
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}
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if (imm)
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shift = IMM(inst) * len;
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else
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shift = *idx_to_addr(regs, RB(inst)) << SV(inst);
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if (regular)
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unaligned_addr += shift;
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if (load) {
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if (!access_ok(VERIFY_READ, (void *)unaligned_addr, len))
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return -EACCES;
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get_data(unaligned_addr, &target_val, len);
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if (sign_ext)
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*idx_to_addr(regs, RT(inst)) =
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sign_extend(target_val, len);
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else
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*idx_to_addr(regs, RT(inst)) = target_val;
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} else {
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if (!access_ok(VERIFY_WRITE, (void *)unaligned_addr, len))
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return -EACCES;
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target_val = *idx_to_addr(regs, RT(inst));
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set_data((void *)unaligned_addr, target_val, len);
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}
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if (!regular)
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*idx_to_addr(regs, RA(inst)) = unaligned_addr + shift;
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regs->ipc += 4;
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return 0;
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fault:
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return -EACCES;
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}
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int do_unaligned_access(unsigned long addr, struct pt_regs *regs)
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{
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unsigned long inst;
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int ret = -EFAULT;
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mm_segment_t seg = get_fs();
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inst = get_inst(regs->ipc);
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DEBUG((unalign_access_debug > 0), 1,
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"Faulting addr: 0x%08lx, pc: 0x%08lx [inst: 0x%08lx ]\n", addr,
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regs->ipc, inst);
|
|
|
|
set_fs(USER_DS);
|
|
|
|
if (inst & NDS32_16BIT_INSTRUCTION)
|
|
ret = do_16((inst >> 16) & 0xffff, regs);
|
|
else
|
|
ret = do_32(inst, regs);
|
|
set_fs(seg);
|
|
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONFIG_PROC_FS
|
|
|
|
static struct ctl_table alignment_tbl[3] = {
|
|
{
|
|
.procname = "enable",
|
|
.data = &unalign_access_mode,
|
|
.maxlen = sizeof(unalign_access_mode),
|
|
.mode = 0666,
|
|
.proc_handler = &proc_dointvec
|
|
}
|
|
,
|
|
{
|
|
.procname = "debug_info",
|
|
.data = &unalign_access_debug,
|
|
.maxlen = sizeof(unalign_access_debug),
|
|
.mode = 0644,
|
|
.proc_handler = &proc_dointvec
|
|
}
|
|
,
|
|
{}
|
|
};
|
|
|
|
static struct ctl_table nds32_sysctl_table[2] = {
|
|
{
|
|
.procname = "unaligned_acess",
|
|
.mode = 0555,
|
|
.child = alignment_tbl},
|
|
{}
|
|
};
|
|
|
|
static struct ctl_path nds32_path[2] = {
|
|
{.procname = "nds32"},
|
|
{}
|
|
};
|
|
|
|
/*
|
|
* Initialize nds32 alignment-correction interface
|
|
*/
|
|
static int __init nds32_sysctl_init(void)
|
|
{
|
|
register_sysctl_paths(nds32_path, nds32_sysctl_table);
|
|
return 0;
|
|
}
|
|
|
|
__initcall(nds32_sysctl_init);
|
|
#endif /* CONFIG_PROC_FS */
|