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29027a1e11
There are only two default memcpy configurations used for the DMA40 driver; one for physical memcpy and one for logical memcpy. Instead of invariably passing the same configurations though platform data, we're moving them into the driver instead. Acked-by: Vinod Koul <vnod.koul@intel.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
229 lines
6.4 KiB
C
229 lines
6.4 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2007-2010
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* Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
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* Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
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* License terms: GNU General Public License (GPL) version 2
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*/
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#ifndef STE_DMA40_H
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#define STE_DMA40_H
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#include <linux/dmaengine.h>
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#include <linux/scatterlist.h>
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#include <linux/workqueue.h>
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#include <linux/interrupt.h>
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/*
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* Maxium size for a single dma descriptor
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* Size is limited to 16 bits.
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* Size is in the units of addr-widths (1,2,4,8 bytes)
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* Larger transfers will be split up to multiple linked desc
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*/
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#define STEDMA40_MAX_SEG_SIZE 0xFFFF
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/* dev types for memcpy */
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#define STEDMA40_DEV_DST_MEMORY (-1)
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#define STEDMA40_DEV_SRC_MEMORY (-1)
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enum stedma40_mode {
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STEDMA40_MODE_LOGICAL = 0,
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STEDMA40_MODE_PHYSICAL,
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STEDMA40_MODE_OPERATION,
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};
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enum stedma40_mode_opt {
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STEDMA40_PCHAN_BASIC_MODE = 0,
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STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,
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STEDMA40_PCHAN_MODULO_MODE,
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STEDMA40_PCHAN_DOUBLE_DST_MODE,
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STEDMA40_LCHAN_SRC_PHY_DST_LOG,
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STEDMA40_LCHAN_SRC_LOG_DST_PHY,
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};
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#define STEDMA40_ESIZE_8_BIT 0x0
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#define STEDMA40_ESIZE_16_BIT 0x1
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#define STEDMA40_ESIZE_32_BIT 0x2
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#define STEDMA40_ESIZE_64_BIT 0x3
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/* The value 4 indicates that PEN-reg shall be set to 0 */
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#define STEDMA40_PSIZE_PHY_1 0x4
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#define STEDMA40_PSIZE_PHY_2 0x0
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#define STEDMA40_PSIZE_PHY_4 0x1
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#define STEDMA40_PSIZE_PHY_8 0x2
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#define STEDMA40_PSIZE_PHY_16 0x3
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/*
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* The number of elements differ in logical and
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* physical mode
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*/
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#define STEDMA40_PSIZE_LOG_1 STEDMA40_PSIZE_PHY_2
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#define STEDMA40_PSIZE_LOG_4 STEDMA40_PSIZE_PHY_4
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#define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8
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#define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16
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/* Maximum number of possible physical channels */
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#define STEDMA40_MAX_PHYS 32
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enum stedma40_flow_ctrl {
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STEDMA40_NO_FLOW_CTRL,
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STEDMA40_FLOW_CTRL,
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};
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enum stedma40_periph_data_width {
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STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
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STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
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STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
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STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
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};
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enum stedma40_xfer_dir {
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STEDMA40_MEM_TO_MEM = 1,
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STEDMA40_MEM_TO_PERIPH,
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STEDMA40_PERIPH_TO_MEM,
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STEDMA40_PERIPH_TO_PERIPH
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};
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/**
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* struct stedma40_chan_cfg - dst/src channel configuration
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*
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* @big_endian: true if the src/dst should be read as big endian
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* @data_width: Data width of the src/dst hardware
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* @p_size: Burst size
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* @flow_ctrl: Flow control on/off.
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*/
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struct stedma40_half_channel_info {
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bool big_endian;
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enum stedma40_periph_data_width data_width;
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int psize;
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enum stedma40_flow_ctrl flow_ctrl;
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};
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/**
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* struct stedma40_chan_cfg - Structure to be filled by client drivers.
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*
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* @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
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* @high_priority: true if high-priority
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* @realtime: true if realtime mode is to be enabled. Only available on DMA40
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* version 3+, i.e DB8500v2+
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* @mode: channel mode: physical, logical, or operation
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* @mode_opt: options for the chosen channel mode
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* @src_dev_type: Src device type
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* @dst_dev_type: Dst device type
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* @src_info: Parameters for dst half channel
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* @dst_info: Parameters for dst half channel
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* @use_fixed_channel: if true, use physical channel specified by phy_channel
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* @phy_channel: physical channel to use, only if use_fixed_channel is true
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*
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* This structure has to be filled by the client drivers.
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* It is recommended to do all dma configurations for clients in the machine.
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*
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*/
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struct stedma40_chan_cfg {
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enum stedma40_xfer_dir dir;
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bool high_priority;
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bool realtime;
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enum stedma40_mode mode;
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enum stedma40_mode_opt mode_opt;
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int src_dev_type;
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int dst_dev_type;
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struct stedma40_half_channel_info src_info;
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struct stedma40_half_channel_info dst_info;
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bool use_fixed_channel;
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int phy_channel;
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};
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/**
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* struct stedma40_platform_data - Configuration struct for the dma device.
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*
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* @dev_len: length of dev_tx and dev_rx
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* @dev_tx: mapping between destination event line and io address
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* @dev_rx: mapping between source event line and io address
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* @disabled_channels: A vector, ending with -1, that marks physical channels
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* that are for different reasons not available for the driver.
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* @soft_lli_chans: A vector, that marks physical channels will use LLI by SW
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* which avoids HW bug that exists in some versions of the controller.
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* SoftLLI introduces relink overhead that could impact performace for
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* certain use cases.
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* @num_of_soft_lli_chans: The number of channels that needs to be configured
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* to use SoftLLI.
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* @use_esram_lcla: flag for mapping the lcla into esram region
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* @num_of_phy_chans: The number of physical channels implemented in HW.
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* 0 means reading the number of channels from DMA HW but this is only valid
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* for 'multiple of 4' channels, like 8.
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*/
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struct stedma40_platform_data {
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u32 dev_len;
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const dma_addr_t *dev_tx;
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const dma_addr_t *dev_rx;
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int disabled_channels[STEDMA40_MAX_PHYS];
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int *soft_lli_chans;
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int num_of_soft_lli_chans;
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bool use_esram_lcla;
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int num_of_phy_chans;
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};
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#ifdef CONFIG_STE_DMA40
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/**
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* stedma40_filter() - Provides stedma40_chan_cfg to the
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* ste_dma40 dma driver via the dmaengine framework.
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* does some checking of what's provided.
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*
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* Never directly called by client. It used by dmaengine.
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* @chan: dmaengine handle.
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* @data: Must be of type: struct stedma40_chan_cfg and is
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* the configuration of the framework.
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*
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*
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*/
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bool stedma40_filter(struct dma_chan *chan, void *data);
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/**
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* stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
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* (=device)
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*
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* @chan: dmaengine handle
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* @addr: source or destination physicall address.
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* @size: bytes to transfer
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* @direction: direction of transfer
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* @flags: is actually enum dma_ctrl_flags. See dmaengine.h
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*/
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static inline struct
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dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
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dma_addr_t addr,
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unsigned int size,
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enum dma_transfer_direction direction,
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unsigned long flags)
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{
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struct scatterlist sg;
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sg_init_table(&sg, 1);
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sg.dma_address = addr;
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sg.length = size;
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return dmaengine_prep_slave_sg(chan, &sg, 1, direction, flags);
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}
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#else
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static inline bool stedma40_filter(struct dma_chan *chan, void *data)
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{
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return false;
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}
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static inline struct
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dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
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dma_addr_t addr,
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unsigned int size,
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enum dma_transfer_direction direction,
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unsigned long flags)
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{
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return NULL;
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}
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#endif
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#endif
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