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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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28b166a700
P4s have a quirk that makes necessary to clear P4_CCCR_OVF bit on the CCCR everytime the PMI is triggered. When booting the kernel with reset_devices (more specific kdump case), the counters reach zero and the PMI will be generated. This is not a problem on other processors but on P4s, it'll continue to generate NMIs until that bit is cleared. Since there may be other users of the performance counters, clear and disable all of them when booting with reset_devices option. We have a P4 box here that crashes because of this problem. Since the kdump kernel usually boots with only one processor active, the second logical unit won't be set up, therefore, MSR_P4_IQ_CCCR1 (and other performance counter registers) won't be cleared and P4_CCCR_OVF may be still set because the previous kernel was using this register. An NMI is triggered because of the MSR_P4_IQ_CCCR1 right after the NMI delivery is enabled, triggering the race fixed on my previous email. Signed-off-by: Aristeu Rozanski <aris@redhat.com> Acked-by: Don Zickus <dzickus@redhat.com> Acked-by: Prarit Bhargava <prarit@redhat.com> Acked-by: Vivek Goyal <vgoyal@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> |
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| .. | ||
| cpufreq | ||
| mcheck | ||
| mtrr | ||
| addon_cpuid_features.c | ||
| amd_64.c | ||
| amd.c | ||
| bugs_64.c | ||
| bugs.c | ||
| centaur_64.c | ||
| centaur.c | ||
| common_64.c | ||
| common.c | ||
| cpu.h | ||
| cyrix.c | ||
| feature_names.c | ||
| intel_64.c | ||
| intel_cacheinfo.c | ||
| intel.c | ||
| Makefile | ||
| perfctr-watchdog.c | ||
| proc.c | ||
| transmeta.c | ||
| umc.c | ||