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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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69d927bba3
Recent probing at the Linux Kernel Memory Model uncovered a
'surprise'. Strongly ordered architectures where the atomic RmW
primitive implies full memory ordering and
smp_mb__{before,after}_atomic() are a simple barrier() (such as x86)
fail for:
*x = 1;
atomic_inc(u);
smp_mb__after_atomic();
r0 = *y;
Because, while the atomic_inc() implies memory order, it
(surprisingly) does not provide a compiler barrier. This then allows
the compiler to re-order like so:
atomic_inc(u);
*x = 1;
smp_mb__after_atomic();
r0 = *y;
Which the CPU is then allowed to re-order (under TSO rules) like:
atomic_inc(u);
r0 = *y;
*x = 1;
And this very much was not intended. Therefore strengthen the atomic
RmW ops to include a compiler barrier.
NOTE: atomic_{or,and,xor} and the bitops already had the compiler
barrier.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
89 lines
2.5 KiB
C
89 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_BARRIER_H
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#define _ASM_X86_BARRIER_H
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#include <asm/alternative.h>
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#include <asm/nops.h>
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/*
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* Force strict CPU ordering.
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* And yes, this might be required on UP too when we're talking
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* to devices.
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*/
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#ifdef CONFIG_X86_32
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#define mb() asm volatile(ALTERNATIVE("lock; addl $0,-4(%%esp)", "mfence", \
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X86_FEATURE_XMM2) ::: "memory", "cc")
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#define rmb() asm volatile(ALTERNATIVE("lock; addl $0,-4(%%esp)", "lfence", \
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X86_FEATURE_XMM2) ::: "memory", "cc")
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#define wmb() asm volatile(ALTERNATIVE("lock; addl $0,-4(%%esp)", "sfence", \
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X86_FEATURE_XMM2) ::: "memory", "cc")
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#else
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#define mb() asm volatile("mfence":::"memory")
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#define rmb() asm volatile("lfence":::"memory")
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#define wmb() asm volatile("sfence" ::: "memory")
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#endif
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/**
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* array_index_mask_nospec() - generate a mask that is ~0UL when the
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* bounds check succeeds and 0 otherwise
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* @index: array element index
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* @size: number of elements in array
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*
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* Returns:
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* 0 - (index < size)
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*/
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static inline unsigned long array_index_mask_nospec(unsigned long index,
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unsigned long size)
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{
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unsigned long mask;
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asm volatile ("cmp %1,%2; sbb %0,%0;"
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:"=r" (mask)
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:"g"(size),"r" (index)
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:"cc");
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return mask;
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}
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/* Override the default implementation from linux/nospec.h. */
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#define array_index_mask_nospec array_index_mask_nospec
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/* Prevent speculative execution past this barrier. */
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#define barrier_nospec() alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC, \
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"lfence", X86_FEATURE_LFENCE_RDTSC)
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#define dma_rmb() barrier()
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#define dma_wmb() barrier()
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#ifdef CONFIG_X86_32
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#define __smp_mb() asm volatile("lock; addl $0,-4(%%esp)" ::: "memory", "cc")
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#else
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#define __smp_mb() asm volatile("lock; addl $0,-4(%%rsp)" ::: "memory", "cc")
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#endif
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#define __smp_rmb() dma_rmb()
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#define __smp_wmb() barrier()
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#define __smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0)
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#define __smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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WRITE_ONCE(*p, v); \
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} while (0)
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#define __smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = READ_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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___p1; \
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})
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/* Atomic operations are already serializing on x86 */
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#define __smp_mb__before_atomic() do { } while (0)
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#define __smp_mb__after_atomic() do { } while (0)
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#include <asm-generic/barrier.h>
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#endif /* _ASM_X86_BARRIER_H */
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