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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e126ba97db
The driver is comprised of two kernel modules: mlx5_ib and mlx5_core. This partitioning resembles what we have for mlx4, except that mlx5_ib is the pci device driver and not mlx5_core. mlx5_core is essentially a library that provides general functionality that is intended to be used by other Mellanox devices that will be introduced in the future. mlx5_ib has a similar role as any hardware device under drivers/infiniband/hw. Signed-off-by: Eli Cohen <eli@mellanox.com> Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il> Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com> [ Merge in coccinelle fixes from Fengguang Wu <fengguang.wu@intel.com>. - Roland ] Signed-off-by: Roland Dreier <roland@purestorage.com>
468 lines
9.8 KiB
C
468 lines
9.8 KiB
C
/*
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* Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef MLX5_QP_H
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#define MLX5_QP_H
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#include <linux/mlx5/device.h>
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#include <linux/mlx5/driver.h>
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#define MLX5_INVALID_LKEY 0x100
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enum mlx5_qp_optpar {
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MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
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MLX5_QP_OPTPAR_RRE = 1 << 1,
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MLX5_QP_OPTPAR_RAE = 1 << 2,
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MLX5_QP_OPTPAR_RWE = 1 << 3,
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MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
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MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
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MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
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MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
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MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
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MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
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MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
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MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
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MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
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MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
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MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
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MLX5_QP_OPTPAR_SRQN = 1 << 18,
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MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
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MLX5_QP_OPTPAR_DC_HS = 1 << 20,
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MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
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};
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enum mlx5_qp_state {
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MLX5_QP_STATE_RST = 0,
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MLX5_QP_STATE_INIT = 1,
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MLX5_QP_STATE_RTR = 2,
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MLX5_QP_STATE_RTS = 3,
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MLX5_QP_STATE_SQER = 4,
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MLX5_QP_STATE_SQD = 5,
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MLX5_QP_STATE_ERR = 6,
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MLX5_QP_STATE_SQ_DRAINING = 7,
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MLX5_QP_STATE_SUSPENDED = 9,
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MLX5_QP_NUM_STATE
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};
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enum {
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MLX5_QP_ST_RC = 0x0,
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MLX5_QP_ST_UC = 0x1,
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MLX5_QP_ST_UD = 0x2,
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MLX5_QP_ST_XRC = 0x3,
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MLX5_QP_ST_MLX = 0x4,
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MLX5_QP_ST_DCI = 0x5,
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MLX5_QP_ST_DCT = 0x6,
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MLX5_QP_ST_QP0 = 0x7,
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MLX5_QP_ST_QP1 = 0x8,
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MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
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MLX5_QP_ST_RAW_IPV6 = 0xa,
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MLX5_QP_ST_SNIFFER = 0xb,
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MLX5_QP_ST_SYNC_UMR = 0xe,
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MLX5_QP_ST_PTP_1588 = 0xd,
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MLX5_QP_ST_REG_UMR = 0xc,
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MLX5_QP_ST_MAX
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};
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enum {
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MLX5_QP_PM_MIGRATED = 0x3,
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MLX5_QP_PM_ARMED = 0x0,
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MLX5_QP_PM_REARM = 0x1
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};
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enum {
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MLX5_NON_ZERO_RQ = 0 << 24,
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MLX5_SRQ_RQ = 1 << 24,
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MLX5_CRQ_RQ = 2 << 24,
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MLX5_ZERO_LEN_RQ = 3 << 24
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};
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enum {
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/* params1 */
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MLX5_QP_BIT_SRE = 1 << 15,
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MLX5_QP_BIT_SWE = 1 << 14,
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MLX5_QP_BIT_SAE = 1 << 13,
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/* params2 */
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MLX5_QP_BIT_RRE = 1 << 15,
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MLX5_QP_BIT_RWE = 1 << 14,
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MLX5_QP_BIT_RAE = 1 << 13,
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MLX5_QP_BIT_RIC = 1 << 4,
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};
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enum {
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MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
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MLX5_WQE_CTRL_SOLICITED = 1 << 1,
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};
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enum {
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MLX5_SEND_WQE_BB = 64,
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};
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enum {
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MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
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MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
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MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
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MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
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MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31
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};
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enum {
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MLX5_FENCE_MODE_NONE = 0 << 5,
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MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
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MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
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MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
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};
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enum {
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MLX5_QP_LAT_SENSITIVE = 1 << 28,
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MLX5_QP_ENABLE_SIG = 1 << 31,
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};
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enum {
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MLX5_RCV_DBR = 0,
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MLX5_SND_DBR = 1,
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};
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struct mlx5_wqe_fmr_seg {
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__be32 flags;
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__be32 mem_key;
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__be64 buf_list;
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__be64 start_addr;
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__be64 reg_len;
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__be32 offset;
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__be32 page_size;
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u32 reserved[2];
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};
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struct mlx5_wqe_ctrl_seg {
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__be32 opmod_idx_opcode;
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__be32 qpn_ds;
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u8 signature;
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u8 rsvd[2];
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u8 fm_ce_se;
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__be32 imm;
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};
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struct mlx5_wqe_xrc_seg {
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__be32 xrc_srqn;
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u8 rsvd[12];
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};
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struct mlx5_wqe_masked_atomic_seg {
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__be64 swap_add;
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__be64 compare;
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__be64 swap_add_mask;
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__be64 compare_mask;
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};
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struct mlx5_av {
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union {
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struct {
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__be32 qkey;
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__be32 reserved;
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} qkey;
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__be64 dc_key;
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} key;
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__be32 dqp_dct;
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u8 stat_rate_sl;
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u8 fl_mlid;
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__be16 rlid;
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u8 reserved0[10];
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u8 tclass;
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u8 hop_limit;
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__be32 grh_gid_fl;
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u8 rgid[16];
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};
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struct mlx5_wqe_datagram_seg {
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struct mlx5_av av;
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};
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struct mlx5_wqe_raddr_seg {
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__be64 raddr;
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__be32 rkey;
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u32 reserved;
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};
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struct mlx5_wqe_atomic_seg {
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__be64 swap_add;
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__be64 compare;
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};
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struct mlx5_wqe_data_seg {
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__be32 byte_count;
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__be32 lkey;
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__be64 addr;
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};
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struct mlx5_wqe_umr_ctrl_seg {
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u8 flags;
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u8 rsvd0[3];
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__be16 klm_octowords;
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__be16 bsf_octowords;
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__be64 mkey_mask;
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u8 rsvd1[32];
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};
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struct mlx5_seg_set_psv {
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__be32 psv_num;
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__be16 syndrome;
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__be16 status;
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__be32 transient_sig;
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__be32 ref_tag;
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};
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struct mlx5_seg_get_psv {
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u8 rsvd[19];
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u8 num_psv;
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__be32 l_key;
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__be64 va;
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__be32 psv_index[4];
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};
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struct mlx5_seg_check_psv {
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u8 rsvd0[2];
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__be16 err_coalescing_op;
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u8 rsvd1[2];
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__be16 xport_err_op;
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u8 rsvd2[2];
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__be16 xport_err_mask;
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u8 rsvd3[7];
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u8 num_psv;
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__be32 l_key;
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__be64 va;
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__be32 psv_index[4];
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};
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struct mlx5_rwqe_sig {
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u8 rsvd0[4];
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u8 signature;
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u8 rsvd1[11];
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};
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struct mlx5_wqe_signature_seg {
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u8 rsvd0[4];
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u8 signature;
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u8 rsvd1[11];
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};
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struct mlx5_wqe_inline_seg {
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__be32 byte_count;
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};
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struct mlx5_core_qp {
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void (*event) (struct mlx5_core_qp *, int);
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int qpn;
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atomic_t refcount;
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struct completion free;
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struct mlx5_rsc_debug *dbg;
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int pid;
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};
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struct mlx5_qp_path {
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u8 fl;
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u8 rsvd3;
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u8 free_ar;
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u8 pkey_index;
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u8 rsvd0;
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u8 grh_mlid;
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__be16 rlid;
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u8 ackto_lt;
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u8 mgid_index;
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u8 static_rate;
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u8 hop_limit;
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__be32 tclass_flowlabel;
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u8 rgid[16];
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u8 rsvd1[4];
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u8 sl;
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u8 port;
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u8 rsvd2[6];
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};
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struct mlx5_qp_context {
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__be32 flags;
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__be32 flags_pd;
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u8 mtu_msgmax;
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u8 rq_size_stride;
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__be16 sq_crq_size;
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__be32 qp_counter_set_usr_page;
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__be32 wire_qpn;
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__be32 log_pg_sz_remote_qpn;
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struct mlx5_qp_path pri_path;
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struct mlx5_qp_path alt_path;
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__be32 params1;
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u8 reserved2[4];
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__be32 next_send_psn;
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__be32 cqn_send;
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u8 reserved3[8];
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__be32 last_acked_psn;
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__be32 ssn;
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__be32 params2;
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__be32 rnr_nextrecvpsn;
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__be32 xrcd;
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__be32 cqn_recv;
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__be64 db_rec_addr;
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__be32 qkey;
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__be32 rq_type_srqn;
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__be32 rmsn;
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__be16 hw_sq_wqe_counter;
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__be16 sw_sq_wqe_counter;
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__be16 hw_rcyclic_byte_counter;
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__be16 hw_rq_counter;
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__be16 sw_rcyclic_byte_counter;
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__be16 sw_rq_counter;
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u8 rsvd0[5];
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u8 cgs;
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u8 cs_req;
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u8 cs_res;
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__be64 dc_access_key;
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u8 rsvd1[24];
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};
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struct mlx5_create_qp_mbox_in {
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struct mlx5_inbox_hdr hdr;
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__be32 input_qpn;
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u8 rsvd0[4];
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__be32 opt_param_mask;
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u8 rsvd1[4];
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struct mlx5_qp_context ctx;
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u8 rsvd3[16];
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__be64 pas[0];
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};
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struct mlx5_create_qp_mbox_out {
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struct mlx5_outbox_hdr hdr;
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__be32 qpn;
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u8 rsvd0[4];
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};
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struct mlx5_destroy_qp_mbox_in {
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struct mlx5_inbox_hdr hdr;
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__be32 qpn;
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u8 rsvd0[4];
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};
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struct mlx5_destroy_qp_mbox_out {
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struct mlx5_outbox_hdr hdr;
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u8 rsvd0[8];
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};
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struct mlx5_modify_qp_mbox_in {
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struct mlx5_inbox_hdr hdr;
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__be32 qpn;
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u8 rsvd1[4];
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__be32 optparam;
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u8 rsvd0[4];
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struct mlx5_qp_context ctx;
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};
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struct mlx5_modify_qp_mbox_out {
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struct mlx5_outbox_hdr hdr;
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u8 rsvd0[8];
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};
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struct mlx5_query_qp_mbox_in {
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struct mlx5_inbox_hdr hdr;
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__be32 qpn;
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u8 rsvd[4];
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};
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struct mlx5_query_qp_mbox_out {
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struct mlx5_outbox_hdr hdr;
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u8 rsvd1[8];
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__be32 optparam;
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u8 rsvd0[4];
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struct mlx5_qp_context ctx;
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u8 rsvd2[16];
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__be64 pas[0];
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};
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struct mlx5_conf_sqp_mbox_in {
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struct mlx5_inbox_hdr hdr;
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__be32 qpn;
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u8 rsvd[3];
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u8 type;
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};
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struct mlx5_conf_sqp_mbox_out {
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struct mlx5_outbox_hdr hdr;
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u8 rsvd[8];
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};
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struct mlx5_alloc_xrcd_mbox_in {
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struct mlx5_inbox_hdr hdr;
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u8 rsvd[8];
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};
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struct mlx5_alloc_xrcd_mbox_out {
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struct mlx5_outbox_hdr hdr;
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__be32 xrcdn;
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u8 rsvd[4];
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};
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struct mlx5_dealloc_xrcd_mbox_in {
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struct mlx5_inbox_hdr hdr;
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__be32 xrcdn;
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u8 rsvd[4];
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};
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struct mlx5_dealloc_xrcd_mbox_out {
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struct mlx5_outbox_hdr hdr;
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u8 rsvd[8];
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};
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static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
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{
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return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
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}
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int mlx5_core_create_qp(struct mlx5_core_dev *dev,
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struct mlx5_core_qp *qp,
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struct mlx5_create_qp_mbox_in *in,
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int inlen);
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int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state,
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enum mlx5_qp_state new_state,
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struct mlx5_modify_qp_mbox_in *in, int sqd_event,
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struct mlx5_core_qp *qp);
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int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
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struct mlx5_core_qp *qp);
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int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
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struct mlx5_query_qp_mbox_out *out, int outlen);
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int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
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int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
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void mlx5_init_qp_table(struct mlx5_core_dev *dev);
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void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
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int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
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void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
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#endif /* MLX5_QP_H */
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