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285541647a
Display register 420B0h bit 22 must be set to 1b for the entire time that Frame Buffer Compression is enabled. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
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