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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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284b965c14
Fam17h and above should not require a check to see if a bank is shared or not. For shared banks, there will always be only one core that has visibility over the MSRs and only that particular core will be allowed to write to the MSRs. Fix the code to return early if we have Scalable MCA support. No change in functionality for earlier processors. Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> [ Massaged the changelog text, fixed kbuild test robot build warning. ] Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1453750913-4781-5-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar <mingo@kernel.org> |
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| .. | ||
| Makefile | ||
| mce_amd.c | ||
| mce_intel.c | ||
| mce-apei.c | ||
| mce-genpool.c | ||
| mce-inject.c | ||
| mce-internal.h | ||
| mce-severity.c | ||
| mce.c | ||
| p5.c | ||
| therm_throt.c | ||
| threshold.c | ||
| winchip.c | ||