mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 01:56:42 +07:00
e241657de0
add playback and capture properties to compatible various chips. Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
668 lines
16 KiB
Plaintext
668 lines
16 KiB
Plaintext
/*
|
|
* Copyright (c) 2013 MundoReader S.L.
|
|
* Author: Heiko Stuebner <heiko@sntech.de>
|
|
*
|
|
* This file is dual-licensed: you can use it either under the terms
|
|
* of the GPL or the X11 license, at your option. Note that this dual
|
|
* licensing only applies to this file, and not this project as a
|
|
* whole.
|
|
*
|
|
* a) This file is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of the
|
|
* License, or (at your option) any later version.
|
|
*
|
|
* This file is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* Or, alternatively,
|
|
*
|
|
* b) Permission is hereby granted, free of charge, to any person
|
|
* obtaining a copy of this software and associated documentation
|
|
* files (the "Software"), to deal in the Software without
|
|
* restriction, including without limitation the rights to use,
|
|
* copy, modify, merge, publish, distribute, sublicense, and/or
|
|
* sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following
|
|
* conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be
|
|
* included in all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
|
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
|
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
|
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
* OTHER DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/pinctrl/rockchip.h>
|
|
#include <dt-bindings/clock/rk3066a-cru.h>
|
|
#include "rk3xxx.dtsi"
|
|
|
|
/ {
|
|
compatible = "rockchip,rk3066a";
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
enable-method = "rockchip,rk3066-smp";
|
|
|
|
cpu0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
next-level-cache = <&L2>;
|
|
reg = <0x0>;
|
|
operating-points = <
|
|
/* kHz uV */
|
|
1008000 1075000
|
|
816000 1025000
|
|
600000 1025000
|
|
504000 1000000
|
|
312000 975000
|
|
>;
|
|
clock-latency = <40000>;
|
|
clocks = <&cru ARMCLK>;
|
|
};
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
next-level-cache = <&L2>;
|
|
reg = <0x1>;
|
|
};
|
|
};
|
|
|
|
sram: sram@10080000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0x10080000 0x10000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x10080000 0x10000>;
|
|
|
|
smp-sram@0 {
|
|
compatible = "rockchip,rk3066-smp-sram";
|
|
reg = <0x0 0x50>;
|
|
};
|
|
};
|
|
|
|
i2s0: i2s@10118000 {
|
|
compatible = "rockchip,rk3066-i2s";
|
|
reg = <0x10118000 0x2000>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s0_bus>;
|
|
dmas = <&dmac1_s 4>, <&dmac1_s 5>;
|
|
dma-names = "tx", "rx";
|
|
clock-names = "i2s_hclk", "i2s_clk";
|
|
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
|
|
rockchip,playback-channels = <8>;
|
|
rockchip,capture-channels = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s1: i2s@1011a000 {
|
|
compatible = "rockchip,rk3066-i2s";
|
|
reg = <0x1011a000 0x2000>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s1_bus>;
|
|
dmas = <&dmac1_s 6>, <&dmac1_s 7>;
|
|
dma-names = "tx", "rx";
|
|
clock-names = "i2s_hclk", "i2s_clk";
|
|
clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
|
|
rockchip,playback-channels = <2>;
|
|
rockchip,capture-channels = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s2: i2s@1011c000 {
|
|
compatible = "rockchip,rk3066-i2s";
|
|
reg = <0x1011c000 0x2000>;
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s2_bus>;
|
|
dmas = <&dmac1_s 9>, <&dmac1_s 10>;
|
|
dma-names = "tx", "rx";
|
|
clock-names = "i2s_hclk", "i2s_clk";
|
|
clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
|
|
rockchip,playback-channels = <2>;
|
|
rockchip,capture-channels = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cru: clock-controller@20000000 {
|
|
compatible = "rockchip,rk3066a-cru";
|
|
reg = <0x20000000 0x1000>;
|
|
rockchip,grf = <&grf>;
|
|
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
timer@2000e000 {
|
|
compatible = "snps,dw-apb-timer-osc";
|
|
reg = <0x2000e000 0x100>;
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
|
|
clock-names = "timer", "pclk";
|
|
};
|
|
|
|
timer@20038000 {
|
|
compatible = "snps,dw-apb-timer-osc";
|
|
reg = <0x20038000 0x100>;
|
|
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
|
|
clock-names = "timer", "pclk";
|
|
};
|
|
|
|
timer@2003a000 {
|
|
compatible = "snps,dw-apb-timer-osc";
|
|
reg = <0x2003a000 0x100>;
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
|
|
clock-names = "timer", "pclk";
|
|
};
|
|
|
|
usbphy: phy {
|
|
compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
|
|
rockchip,grf = <&grf>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
usbphy0: usb-phy0 {
|
|
#phy-cells = <0>;
|
|
reg = <0x17c>;
|
|
clocks = <&cru SCLK_OTGPHY0>;
|
|
clock-names = "phyclk";
|
|
};
|
|
|
|
usbphy1: usb-phy1 {
|
|
#phy-cells = <0>;
|
|
reg = <0x188>;
|
|
clocks = <&cru SCLK_OTGPHY1>;
|
|
clock-names = "phyclk";
|
|
};
|
|
};
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "rockchip,rk3066a-pinctrl";
|
|
rockchip,grf = <&grf>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
gpio0: gpio0@20034000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x20034000 0x100>;
|
|
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO0>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio1: gpio1@2003c000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x2003c000 0x100>;
|
|
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO1>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio2@2003e000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x2003e000 0x100>;
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO2>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio3@20080000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x20080000 0x100>;
|
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO3>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio4: gpio4@20084000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x20084000 0x100>;
|
|
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO4>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio6: gpio6@2000a000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x2000a000 0x100>;
|
|
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO6>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
pcfg_pull_default: pcfg_pull_default {
|
|
bias-pull-pin-default;
|
|
};
|
|
|
|
pcfg_pull_none: pcfg_pull_none {
|
|
bias-disable;
|
|
};
|
|
|
|
emac {
|
|
emac_xfer: emac-xfer {
|
|
rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
|
|
<RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
|
|
<RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
|
|
<RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
|
|
<RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
|
|
<RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
|
|
<RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
|
|
<RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
|
|
};
|
|
|
|
emac_mdio: emac-mdio {
|
|
rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
|
|
<RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
|
|
};
|
|
};
|
|
|
|
emmc {
|
|
emmc_clk: emmc-clk {
|
|
rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
|
|
};
|
|
|
|
emmc_cmd: emmc-cmd {
|
|
rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
|
|
};
|
|
|
|
emmc_rst: emmc-rst {
|
|
rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
|
|
};
|
|
|
|
/*
|
|
* The data pins are shared between nandc and emmc and
|
|
* not accessible through pinctrl. Also they should've
|
|
* been already set correctly by firmware, as
|
|
* flash/emmc is the boot-device.
|
|
*/
|
|
};
|
|
|
|
i2c0 {
|
|
i2c0_xfer: i2c0-xfer {
|
|
rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c1 {
|
|
i2c1_xfer: i2c1-xfer {
|
|
rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c2 {
|
|
i2c2_xfer: i2c2-xfer {
|
|
rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c3 {
|
|
i2c3_xfer: i2c3-xfer {
|
|
rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
|
|
<RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c4 {
|
|
i2c4_xfer: i2c4-xfer {
|
|
rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm0 {
|
|
pwm0_out: pwm0-out {
|
|
rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm1 {
|
|
pwm1_out: pwm1-out {
|
|
rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm2 {
|
|
pwm2_out: pwm2-out {
|
|
rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm3 {
|
|
pwm3_out: pwm3-out {
|
|
rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spi0 {
|
|
spi0_clk: spi0-clk {
|
|
rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
|
|
};
|
|
spi0_cs0: spi0-cs0 {
|
|
rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
|
|
};
|
|
spi0_tx: spi0-tx {
|
|
rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
|
|
};
|
|
spi0_rx: spi0-rx {
|
|
rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
|
|
};
|
|
spi0_cs1: spi0-cs1 {
|
|
rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
};
|
|
|
|
spi1 {
|
|
spi1_clk: spi1-clk {
|
|
rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
|
|
};
|
|
spi1_cs0: spi1-cs0 {
|
|
rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
|
|
};
|
|
spi1_rx: spi1-rx {
|
|
rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
|
|
};
|
|
spi1_tx: spi1-tx {
|
|
rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
|
|
};
|
|
spi1_cs1: spi1-cs1 {
|
|
rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
uart0_xfer: uart0-xfer {
|
|
rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
|
|
uart0_cts: uart0-cts {
|
|
rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
|
|
uart0_rts: uart0-rts {
|
|
rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
uart1_xfer: uart1-xfer {
|
|
rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
|
|
uart1_cts: uart1-cts {
|
|
rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
|
|
uart1_rts: uart1-rts {
|
|
rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
};
|
|
|
|
uart2 {
|
|
uart2_xfer: uart2-xfer {
|
|
rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
/* no rts / cts for uart2 */
|
|
};
|
|
|
|
uart3 {
|
|
uart3_xfer: uart3-xfer {
|
|
rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
|
|
uart3_cts: uart3-cts {
|
|
rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
|
|
uart3_rts: uart3-rts {
|
|
rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
};
|
|
|
|
sd0 {
|
|
sd0_clk: sd0-clk {
|
|
rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
|
|
sd0_cmd: sd0-cmd {
|
|
rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
|
|
sd0_cd: sd0-cd {
|
|
rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
|
|
sd0_wp: sd0-wp {
|
|
rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
|
|
sd0_bus1: sd0-bus-width1 {
|
|
rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
|
|
sd0_bus4: sd0-bus-width4 {
|
|
rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
};
|
|
|
|
sd1 {
|
|
sd1_clk: sd1-clk {
|
|
rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
|
|
sd1_cmd: sd1-cmd {
|
|
rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
|
|
sd1_cd: sd1-cd {
|
|
rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
|
|
sd1_wp: sd1-wp {
|
|
rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
|
|
sd1_bus1: sd1-bus-width1 {
|
|
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
|
|
sd1_bus4: sd1-bus-width4 {
|
|
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
};
|
|
|
|
i2s0 {
|
|
i2s0_bus: i2s0-bus {
|
|
rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
};
|
|
|
|
i2s1 {
|
|
i2s1_bus: i2s1-bus {
|
|
rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
};
|
|
|
|
i2s2 {
|
|
i2s2_bus: i2s2-bus {
|
|
rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
|
|
<RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_xfer>;
|
|
};
|
|
|
|
&i2c1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_xfer>;
|
|
};
|
|
|
|
&i2c2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_xfer>;
|
|
};
|
|
|
|
&i2c3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3_xfer>;
|
|
};
|
|
|
|
&i2c4 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4_xfer>;
|
|
};
|
|
|
|
&mmc0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
|
|
};
|
|
|
|
&mmc1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
|
|
};
|
|
|
|
&pwm0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm0_out>;
|
|
};
|
|
|
|
&pwm1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm1_out>;
|
|
};
|
|
|
|
&pwm2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm2_out>;
|
|
};
|
|
|
|
&pwm3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm3_out>;
|
|
};
|
|
|
|
&spi0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
|
|
};
|
|
|
|
&spi1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
|
|
};
|
|
|
|
&uart0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart0_xfer>;
|
|
};
|
|
|
|
&uart1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart1_xfer>;
|
|
};
|
|
|
|
&uart2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart2_xfer>;
|
|
};
|
|
|
|
&uart3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart3_xfer>;
|
|
};
|
|
|
|
&wdt {
|
|
compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
|
|
};
|
|
|
|
&emac {
|
|
compatible = "rockchip,rk3066-emac";
|
|
};
|