mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 01:56:42 +07:00
c175e7abf7
22b160713c ("ARM: shmobile: alt: Add pfc pins to DT") introduced pfc pins
to the alt device tree but did not reference them. This patch fixes ether
pfc by:
* Referencing ether pins
* Adding and referencing phy1 pins
* Removing ether b pins. These are not used in the configuration
of the alt board used for testing and empirically their presence
prevents ethernet from functioning correctly in that environment.
Reported-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
200 lines
3.2 KiB
Plaintext
200 lines
3.2 KiB
Plaintext
/*
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* Device Tree Source for the Alt board
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*
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* Copyright (C) 2014 Renesas Electronics Corporation
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/dts-v1/;
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#include "r8a7794.dtsi"
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/ {
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model = "Alt";
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compatible = "renesas,alt", "renesas,r8a7794";
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aliases {
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serial0 = &scif2;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
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stdout-path = &scif2;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x40000000>;
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};
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lbsc {
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#address-cells = <1>;
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#size-cells = <1>;
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};
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vga-encoder {
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compatible = "adi,adv7123";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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adv7123_in: endpoint {
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remote-endpoint = <&du_out_rgb1>;
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};
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};
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port@1 {
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reg = <1>;
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adv7123_out: endpoint {
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remote-endpoint = <&vga_in>;
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};
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};
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};
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};
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vga {
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compatible = "vga-connector";
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port {
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vga_in: endpoint {
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remote-endpoint = <&adv7123_out>;
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};
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};
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};
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x2_clk: x2-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <74250000>;
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};
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x13_clk: x13-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <148500000>;
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};
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};
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&du {
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pinctrl-0 = <&du_pins>;
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pinctrl-names = "default";
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status = "okay";
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clocks = <&mstp7_clks R8A7794_CLK_DU0>,
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<&mstp7_clks R8A7794_CLK_DU0>,
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<&x13_clk>, <&x2_clk>;
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clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
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ports {
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port@1 {
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endpoint {
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remote-endpoint = <&adv7123_in>;
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};
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};
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};
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};
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&extal_clk {
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clock-frequency = <20000000>;
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};
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&pfc {
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du_pins: du {
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renesas,groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
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renesas,function = "du";
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};
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scif2_pins: serial2 {
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renesas,groups = "scif2_data";
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renesas,function = "scif2";
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};
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ether_pins: ether {
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renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
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renesas,function = "eth";
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};
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phy1_pins: phy1 {
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renesas,groups = "intc_irq8";
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renesas,function = "intc";
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};
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i2c1_pins: i2c1 {
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renesas,groups = "i2c1";
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renesas,function = "i2c1";
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};
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vin0_pins: vin0 {
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renesas,groups = "vin0_data8", "vin0_clk";
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renesas,function = "vin0";
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};
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};
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&cmt0 {
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status = "okay";
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};
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ðer {
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pinctrl-0 = <ðer_pins &phy1_pins>;
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pinctrl-names = "default";
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phy-handle = <&phy1>;
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renesas,ether-link-active-low;
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status = "okay";
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phy1: ethernet-phy@1 {
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reg = <1>;
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interrupt-parent = <&irqc0>;
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interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
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micrel,led-mode = <1>;
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};
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};
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&i2c1 {
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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status = "okay";
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clock-frequency = <400000>;
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composite-in@20 {
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compatible = "adi,adv7180";
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reg = <0x20>;
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remote = <&vin0>;
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port {
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adv7180: endpoint {
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bus-width = <8>;
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remote-endpoint = <&vin0ep>;
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};
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};
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};
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};
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&vin0 {
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status = "okay";
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pinctrl-0 = <&vin0_pins>;
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pinctrl-names = "default";
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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vin0ep: endpoint {
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remote-endpoint = <&adv7180>;
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bus-width = <8>;
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};
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};
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};
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&scif2 {
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pinctrl-0 = <&scif2_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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