mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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281b05392f
These changes are all specific to an soc family or the code for one soc. Lots of work for Tegra3 this time, but also a lot of other platforms. There will be another (smaller) set of soc patches later in the merge window for stuff that has dependencies on external trees or that was sent just before the merge window opened. The asoc tree added a few devices to the i.mx platform, which conflict with other devices added in the same place here. The tegra Makefile conflicts between a number of branches, mostly because of changes regarding localtimer.c, which was removed in the end. Signed-off-by: Arnd Bergmann <arnd@arndb.de> -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIVAwUAT24+62CrR//JCVInAQLQBQ/8ClDSFYKTkh3XuzryyO3xkiuuj9wp3/av oEzro6HmSFDeWlqyQYYM9nKn6n3zFyyumG7oHt3OyRwrtV742rMOpTK+/Ntj2lFB xUVwKQfu2gEMHvwca3VoXia/pX7knvedEf9bNjeCznkKxQCKCArK2821/2UDGhwx L3/lD70AhpfK0DInNr6HusnZG2pzCdV1tLXUvgs08I68wL7Ps1TDPOLLyTo9dAgf k+E1cpRNLahyiVUBfnp+n3Dg0T+/7iD6zrR7bE9i/zhv6XUcLPt2K5XqYnPuQvzK sHIG8zROmNWzaIzgwYVpJAofi0SHq1OjvA7RtepOq/pGe5QvB9y1RISlpwzBr6Fh 4yuBkeN/Azk0xSHw5w++8L4y/oSSNhB9OWgIZGChZMW33bnHyiZW9mDFJ/PyWD0F kRl++tTuQqDvT5Wx4DXX8RGekIiFq48+MMx3yJjuGarmVsPEvShQCf8TkBbl/KQY /AEXMJTaVTED0R/q+NOY/r4oMFC4JtAVo1ZtTga+N5cYWQCwI9HVSgAKw84Yc1Hj h9r7XjDhmGYFWMfWe9V5NtFNmXl6tAo66fMzSG6+9k+UEXiF1WrhnzBuks5zFU7z z4WBRL0GmaNBdq58dJoM4lucnuhhQk2m7wz5Lt4o17enw0dAfSXQMstDMnbE7c51 65yZh8o9mxs= =WdYR -----END PGP SIGNATURE----- Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull "ARM: SoC specific updates" from Arnd Bergmann: "These changes are all specific to an soc family or the code for one soc. Lots of work for Tegra3 this time, but also a lot of other platforms. There will be another (smaller) set of soc patches later in the merge window for stuff that has dependencies on external trees or that was sent just before the merge window opened. The asoc tree added a few devices to the i.mx platform, which conflict with other devices added in the same place here. The tegra Makefile conflicts between a number of branches, mostly because of changes regarding localtimer.c, which was removed in the end. Signed-off-by: Arnd Bergmann <arnd@arndb.de>" Fix up some trivial conflicts, including the mentioned Tegra Makefile. * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (51 commits) ARM: EXYNOS: fix cycle count for periodic mode of clock event timers ARM: EXYNOS: add support JPEG ARM: EXYNOS: Add DMC1, allow PPMU access for DMC ARM: SAMSUNG: Correct MIPI-CSIS io memory resource definition ARM: SAMSUNG: fix __init attribute on regarding s3c_set_platdata() ARM: SAMSUNG: Add __init attribute to samsung_bl_set() ARM: S5PV210: Add usb otg phy control ARM: S3C64XX: Add usb otg phy control ARM: EXYNOS: Enable l2 configuration through device tree ARM: EXYNOS: remove useless code to save/restore L2 ARM: EXYNOS: save L2 settings during bootup ARM: S5P: add L2 early resume code ARM: EXYNOS: Add support AFTR mode on EXYNOS4210 ARM: mx35: Setup the AIPS registers ARM: mx5: Use common function for configuring AIPS ARM: mx3: Setup AIPS registers ARM: mx3: Let mx31 and mx35 enter in LPM mode in WFI ARM: defconfig: imx_v6_v7: build in REGULATOR_FIXED_VOLTAGE ARM: imx: update imx_v6_v7_defconfig ARM: tegra: Demote EMC clock inconsistency BUG to WARN ...
153 lines
3.7 KiB
C
153 lines
3.7 KiB
C
/*
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* Copyright 2010-2011 Calxeda, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include <asm/smp_twd.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/hardware/timer-sp.h>
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#include <asm/hardware/gic.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <mach/irqs.h>
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#include "core.h"
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#include "sysregs.h"
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void __iomem *sregs_base;
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#define HB_SCU_VIRT_BASE 0xfee00000
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void __iomem *scu_base_addr = ((void __iomem *)(HB_SCU_VIRT_BASE));
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static struct map_desc scu_io_desc __initdata = {
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.virtual = HB_SCU_VIRT_BASE,
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.pfn = 0, /* run-time */
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.length = SZ_4K,
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.type = MT_DEVICE,
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};
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static void __init highbank_scu_map_io(void)
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{
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unsigned long base;
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/* Get SCU base */
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asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
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scu_io_desc.pfn = __phys_to_pfn(base);
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iotable_init(&scu_io_desc, 1);
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}
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static void __init highbank_map_io(void)
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{
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highbank_scu_map_io();
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highbank_lluart_map_io();
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}
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#define HB_JUMP_TABLE_PHYS(cpu) (0x40 + (0x10 * (cpu)))
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#define HB_JUMP_TABLE_VIRT(cpu) phys_to_virt(HB_JUMP_TABLE_PHYS(cpu))
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void highbank_set_cpu_jump(int cpu, void *jump_addr)
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{
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cpu = cpu_logical_map(cpu);
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writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu));
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__cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
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outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
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HB_JUMP_TABLE_PHYS(cpu) + 15);
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}
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const static struct of_device_id irq_match[] = {
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{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
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{}
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};
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static void __init highbank_init_irq(void)
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{
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of_irq_init(irq_match);
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l2x0_of_init(0, ~0UL);
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}
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static void __init highbank_timer_init(void)
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{
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int irq;
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struct device_node *np;
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void __iomem *timer_base;
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/* Map system registers */
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np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
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sregs_base = of_iomap(np, 0);
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WARN_ON(!sregs_base);
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np = of_find_compatible_node(NULL, NULL, "arm,sp804");
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timer_base = of_iomap(np, 0);
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WARN_ON(!timer_base);
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irq = irq_of_parse_and_map(np, 0);
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highbank_clocks_init();
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sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1");
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sp804_clockevents_init(timer_base, irq, "timer0");
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twd_local_timer_of_register();
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}
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static struct sys_timer highbank_timer = {
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.init = highbank_timer_init,
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};
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static void highbank_power_off(void)
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{
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hignbank_set_pwr_shutdown();
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scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
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while (1)
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cpu_do_idle();
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}
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static void __init highbank_init(void)
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{
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pm_power_off = highbank_power_off;
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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}
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static const char *highbank_match[] __initconst = {
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"calxeda,highbank",
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NULL,
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};
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DT_MACHINE_START(HIGHBANK, "Highbank")
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.map_io = highbank_map_io,
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.init_irq = highbank_init_irq,
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.timer = &highbank_timer,
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.handle_irq = gic_handle_irq,
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.init_machine = highbank_init,
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.dt_compat = highbank_match,
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.restart = highbank_restart,
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MACHINE_END
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