mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 20:15:13 +07:00
94c70241ef
Rather than always using handle_simple_irq() as the gpio_irq_chip handler, set a more appropriate handler based on the IRQ trigger type requested. This is important for level triggered interrupts which need to be masked during handling. Also, fix the interrupt acknowledge so that it clears only one interrupt instead of all interrupts which are currently active. Finally there is no need to clear the interrupt during the interrupt handler, since the edge-triggered handler will do that for us. Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Link: https://lore.kernel.org/r/20200703011830.15655-1-mark.tomlinson@alliedtelesis.co.nz Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
725 lines
18 KiB
C
725 lines
18 KiB
C
/*
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* Copyright (C) 2014-2017 Broadcom
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* This file contains the Broadcom Northstar Plus (NSP) GPIO driver that
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* supports the chipCommonA GPIO controller. Basic PINCONF such as bias,
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* pull up/down, slew and drive strength are also supported in this driver.
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*
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* Pins from the chipCommonA GPIO can be individually muxed to GPIO function,
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* through the interaction with the NSP IOMUX controller.
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*/
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#include <linux/gpio/driver.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/slab.h>
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#include "../pinctrl-utils.h"
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#define NSP_CHIP_A_INT_STATUS 0x00
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#define NSP_CHIP_A_INT_MASK 0x04
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#define NSP_GPIO_DATA_IN 0x40
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#define NSP_GPIO_DATA_OUT 0x44
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#define NSP_GPIO_OUT_EN 0x48
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#define NSP_GPIO_INT_POLARITY 0x50
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#define NSP_GPIO_INT_MASK 0x54
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#define NSP_GPIO_EVENT 0x58
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#define NSP_GPIO_EVENT_INT_MASK 0x5c
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#define NSP_GPIO_EVENT_INT_POLARITY 0x64
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#define NSP_CHIP_A_GPIO_INT_BIT 0x01
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/* I/O parameters offset for chipcommon A GPIO */
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#define NSP_GPIO_DRV_CTRL 0x00
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#define NSP_GPIO_HYSTERESIS_EN 0x10
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#define NSP_GPIO_SLEW_RATE_EN 0x14
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#define NSP_PULL_UP_EN 0x18
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#define NSP_PULL_DOWN_EN 0x1c
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#define GPIO_DRV_STRENGTH_BITS 0x03
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/*
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* nsp GPIO core
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*
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* @dev: pointer to device
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* @base: I/O register base for nsp GPIO controller
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* @io_ctrl: I/O register base for PINCONF support outside the GPIO block
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* @gc: GPIO chip
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* @pctl: pointer to pinctrl_dev
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* @pctldesc: pinctrl descriptor
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* @lock: lock to protect access to I/O registers
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*/
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struct nsp_gpio {
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struct device *dev;
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void __iomem *base;
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void __iomem *io_ctrl;
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struct irq_chip irqchip;
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struct gpio_chip gc;
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struct pinctrl_dev *pctl;
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struct pinctrl_desc pctldesc;
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raw_spinlock_t lock;
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};
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enum base_type {
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REG,
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IO_CTRL
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};
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/*
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* Mapping from PINCONF pins to GPIO pins is 1-to-1
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*/
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static inline unsigned nsp_pin_to_gpio(unsigned pin)
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{
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return pin;
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}
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/*
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* nsp_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
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* nsp GPIO register
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*
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* @nsp_gpio: nsp GPIO device
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* @base_type: reg base to modify
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* @reg: register offset
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* @gpio: GPIO pin
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* @set: set or clear
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*/
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static inline void nsp_set_bit(struct nsp_gpio *chip, enum base_type address,
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unsigned int reg, unsigned gpio, bool set)
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{
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u32 val;
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void __iomem *base_address;
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if (address == IO_CTRL)
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base_address = chip->io_ctrl;
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else
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base_address = chip->base;
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val = readl(base_address + reg);
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if (set)
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val |= BIT(gpio);
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else
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val &= ~BIT(gpio);
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writel(val, base_address + reg);
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}
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/*
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* nsp_get_bit - get one bit (corresponding to the GPIO pin) in a
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* nsp GPIO register
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*/
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static inline bool nsp_get_bit(struct nsp_gpio *chip, enum base_type address,
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unsigned int reg, unsigned gpio)
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{
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if (address == IO_CTRL)
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return !!(readl(chip->io_ctrl + reg) & BIT(gpio));
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else
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return !!(readl(chip->base + reg) & BIT(gpio));
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}
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static irqreturn_t nsp_gpio_irq_handler(int irq, void *data)
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{
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struct gpio_chip *gc = (struct gpio_chip *)data;
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struct nsp_gpio *chip = gpiochip_get_data(gc);
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int bit;
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unsigned long int_bits = 0;
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u32 int_status;
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/* go through the entire GPIOs and handle all interrupts */
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int_status = readl(chip->base + NSP_CHIP_A_INT_STATUS);
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if (int_status & NSP_CHIP_A_GPIO_INT_BIT) {
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unsigned int event, level;
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/* Get level and edge interrupts */
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event = readl(chip->base + NSP_GPIO_EVENT_INT_MASK) &
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readl(chip->base + NSP_GPIO_EVENT);
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level = readl(chip->base + NSP_GPIO_DATA_IN) ^
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readl(chip->base + NSP_GPIO_INT_POLARITY);
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level &= readl(chip->base + NSP_GPIO_INT_MASK);
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int_bits = level | event;
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for_each_set_bit(bit, &int_bits, gc->ngpio)
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generic_handle_irq(
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irq_linear_revmap(gc->irq.domain, bit));
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}
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return int_bits ? IRQ_HANDLED : IRQ_NONE;
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}
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static void nsp_gpio_irq_ack(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct nsp_gpio *chip = gpiochip_get_data(gc);
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unsigned gpio = d->hwirq;
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u32 val = BIT(gpio);
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u32 trigger_type;
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trigger_type = irq_get_trigger_type(d->irq);
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if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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writel(val, chip->base + NSP_GPIO_EVENT);
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}
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/*
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* nsp_gpio_irq_set_mask - mask/unmask a GPIO interrupt
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*
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* @d: IRQ chip data
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* @unmask: mask/unmask GPIO interrupt
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*/
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static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct nsp_gpio *chip = gpiochip_get_data(gc);
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unsigned gpio = d->hwirq;
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u32 trigger_type;
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trigger_type = irq_get_trigger_type(d->irq);
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if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask);
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else
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nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask);
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}
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static void nsp_gpio_irq_mask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct nsp_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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raw_spin_lock_irqsave(&chip->lock, flags);
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nsp_gpio_irq_set_mask(d, false);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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}
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static void nsp_gpio_irq_unmask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct nsp_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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raw_spin_lock_irqsave(&chip->lock, flags);
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nsp_gpio_irq_set_mask(d, true);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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}
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static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct nsp_gpio *chip = gpiochip_get_data(gc);
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unsigned gpio = d->hwirq;
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bool level_low;
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bool falling;
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unsigned long flags;
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raw_spin_lock_irqsave(&chip->lock, flags);
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falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio);
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level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio);
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_RISING:
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falling = false;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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falling = true;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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level_low = false;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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level_low = true;
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break;
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default:
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dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
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type);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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return -EINVAL;
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}
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nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling);
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nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low);
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if (type & IRQ_TYPE_EDGE_BOTH)
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irq_set_handler_locked(d, handle_edge_irq);
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else
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irq_set_handler_locked(d, handle_level_irq);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio,
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level_low ? "true" : "false", falling ? "true" : "false");
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return 0;
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}
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static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
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{
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struct nsp_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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raw_spin_lock_irqsave(&chip->lock, flags);
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nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
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return 0;
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}
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static int nsp_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
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int val)
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{
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struct nsp_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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raw_spin_lock_irqsave(&chip->lock, flags);
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nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true);
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nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
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return 0;
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}
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static int nsp_gpio_get_direction(struct gpio_chip *gc, unsigned gpio)
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{
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struct nsp_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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int val;
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raw_spin_lock_irqsave(&chip->lock, flags);
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val = nsp_get_bit(chip, REG, NSP_GPIO_OUT_EN, gpio);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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return !val;
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}
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static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
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{
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struct nsp_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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raw_spin_lock_irqsave(&chip->lock, flags);
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nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
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}
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static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio)
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{
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struct nsp_gpio *chip = gpiochip_get_data(gc);
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return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio));
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}
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static int nsp_get_groups_count(struct pinctrl_dev *pctldev)
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{
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return 1;
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}
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/*
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* Only one group: "gpio_grp", since this local pinctrl device only performs
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* GPIO specific PINCONF configurations
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*/
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static const char *nsp_get_group_name(struct pinctrl_dev *pctldev,
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unsigned selector)
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{
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return "gpio_grp";
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}
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static const struct pinctrl_ops nsp_pctrl_ops = {
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.get_groups_count = nsp_get_groups_count,
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.get_group_name = nsp_get_group_name,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
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.dt_free_map = pinctrl_utils_free_map,
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};
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static int nsp_gpio_set_slew(struct nsp_gpio *chip, unsigned gpio, u32 slew)
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{
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if (slew)
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nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, true);
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else
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nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, false);
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return 0;
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}
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static int nsp_gpio_set_pull(struct nsp_gpio *chip, unsigned gpio,
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bool pull_up, bool pull_down)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&chip->lock, flags);
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nsp_set_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio, pull_down);
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nsp_set_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio, pull_up);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set pullup:%d pulldown: %d\n",
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gpio, pull_up, pull_down);
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return 0;
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}
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static void nsp_gpio_get_pull(struct nsp_gpio *chip, unsigned gpio,
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bool *pull_up, bool *pull_down)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&chip->lock, flags);
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*pull_up = nsp_get_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio);
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*pull_down = nsp_get_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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}
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static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio,
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u32 strength)
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{
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u32 offset, shift, i;
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u32 val;
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unsigned long flags;
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/* make sure drive strength is supported */
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if (strength < 2 || strength > 16 || (strength % 2))
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return -ENOTSUPP;
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shift = gpio;
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offset = NSP_GPIO_DRV_CTRL;
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dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
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strength);
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raw_spin_lock_irqsave(&chip->lock, flags);
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strength = (strength / 2) - 1;
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for (i = GPIO_DRV_STRENGTH_BITS; i > 0; i--) {
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val = readl(chip->io_ctrl + offset);
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val &= ~BIT(shift);
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val |= ((strength >> (i-1)) & 0x1) << shift;
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writel(val, chip->io_ctrl + offset);
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offset += 4;
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}
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio,
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u16 *strength)
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{
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unsigned int offset, shift;
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u32 val;
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unsigned long flags;
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int i;
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offset = NSP_GPIO_DRV_CTRL;
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shift = gpio;
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raw_spin_lock_irqsave(&chip->lock, flags);
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*strength = 0;
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for (i = (GPIO_DRV_STRENGTH_BITS - 1); i >= 0; i--) {
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val = readl(chip->io_ctrl + offset) & BIT(shift);
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val >>= shift;
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*strength += (val << i);
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offset += 4;
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}
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/* convert to mA */
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*strength = (*strength + 1) * 2;
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static int nsp_pin_config_group_get(struct pinctrl_dev *pctldev,
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unsigned selector,
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unsigned long *config)
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{
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return 0;
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}
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static int nsp_pin_config_group_set(struct pinctrl_dev *pctldev,
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unsigned selector,
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unsigned long *configs, unsigned num_configs)
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{
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return 0;
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}
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static int nsp_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
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unsigned long *config)
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{
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struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
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enum pin_config_param param = pinconf_to_config_param(*config);
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unsigned int gpio;
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u16 arg = 0;
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bool pull_up, pull_down;
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int ret;
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gpio = nsp_pin_to_gpio(pin);
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
|
|
nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
|
|
if ((pull_up == false) && (pull_down == false))
|
|
return 0;
|
|
else
|
|
return -EINVAL;
|
|
|
|
case PIN_CONFIG_BIAS_PULL_UP:
|
|
nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
|
|
if (pull_up)
|
|
return 0;
|
|
else
|
|
return -EINVAL;
|
|
|
|
case PIN_CONFIG_BIAS_PULL_DOWN:
|
|
nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
|
|
if (pull_down)
|
|
return 0;
|
|
else
|
|
return -EINVAL;
|
|
|
|
case PIN_CONFIG_DRIVE_STRENGTH:
|
|
ret = nsp_gpio_get_strength(chip, gpio, &arg);
|
|
if (ret)
|
|
return ret;
|
|
*config = pinconf_to_config_packed(param, arg);
|
|
return 0;
|
|
|
|
default:
|
|
return -ENOTSUPP;
|
|
}
|
|
}
|
|
|
|
static int nsp_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
|
|
unsigned long *configs, unsigned num_configs)
|
|
{
|
|
struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
|
|
enum pin_config_param param;
|
|
u32 arg;
|
|
unsigned int i, gpio;
|
|
int ret = -ENOTSUPP;
|
|
|
|
gpio = nsp_pin_to_gpio(pin);
|
|
for (i = 0; i < num_configs; i++) {
|
|
param = pinconf_to_config_param(configs[i]);
|
|
arg = pinconf_to_config_argument(configs[i]);
|
|
|
|
switch (param) {
|
|
case PIN_CONFIG_BIAS_DISABLE:
|
|
ret = nsp_gpio_set_pull(chip, gpio, false, false);
|
|
if (ret < 0)
|
|
goto out;
|
|
break;
|
|
|
|
case PIN_CONFIG_BIAS_PULL_UP:
|
|
ret = nsp_gpio_set_pull(chip, gpio, true, false);
|
|
if (ret < 0)
|
|
goto out;
|
|
break;
|
|
|
|
case PIN_CONFIG_BIAS_PULL_DOWN:
|
|
ret = nsp_gpio_set_pull(chip, gpio, false, true);
|
|
if (ret < 0)
|
|
goto out;
|
|
break;
|
|
|
|
case PIN_CONFIG_DRIVE_STRENGTH:
|
|
ret = nsp_gpio_set_strength(chip, gpio, arg);
|
|
if (ret < 0)
|
|
goto out;
|
|
break;
|
|
|
|
case PIN_CONFIG_SLEW_RATE:
|
|
ret = nsp_gpio_set_slew(chip, gpio, arg);
|
|
if (ret < 0)
|
|
goto out;
|
|
break;
|
|
|
|
default:
|
|
dev_err(chip->dev, "invalid configuration\n");
|
|
return -ENOTSUPP;
|
|
}
|
|
}
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static const struct pinconf_ops nsp_pconf_ops = {
|
|
.is_generic = true,
|
|
.pin_config_get = nsp_pin_config_get,
|
|
.pin_config_set = nsp_pin_config_set,
|
|
.pin_config_group_get = nsp_pin_config_group_get,
|
|
.pin_config_group_set = nsp_pin_config_group_set,
|
|
};
|
|
|
|
/*
|
|
* NSP GPIO controller supports some PINCONF related configurations such as
|
|
* pull up, pull down, slew and drive strength, when the pin is configured
|
|
* to GPIO.
|
|
*
|
|
* Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
|
|
* local GPIO pins
|
|
*/
|
|
static int nsp_gpio_register_pinconf(struct nsp_gpio *chip)
|
|
{
|
|
struct pinctrl_desc *pctldesc = &chip->pctldesc;
|
|
struct pinctrl_pin_desc *pins;
|
|
struct gpio_chip *gc = &chip->gc;
|
|
int i;
|
|
|
|
pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
|
|
if (!pins)
|
|
return -ENOMEM;
|
|
for (i = 0; i < gc->ngpio; i++) {
|
|
pins[i].number = i;
|
|
pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
|
|
"gpio-%d", i);
|
|
if (!pins[i].name)
|
|
return -ENOMEM;
|
|
}
|
|
pctldesc->name = dev_name(chip->dev);
|
|
pctldesc->pctlops = &nsp_pctrl_ops;
|
|
pctldesc->pins = pins;
|
|
pctldesc->npins = gc->ngpio;
|
|
pctldesc->confops = &nsp_pconf_ops;
|
|
|
|
chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
|
|
if (IS_ERR(chip->pctl)) {
|
|
dev_err(chip->dev, "unable to register pinctrl device\n");
|
|
return PTR_ERR(chip->pctl);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id nsp_gpio_of_match[] = {
|
|
{.compatible = "brcm,nsp-gpio-a",},
|
|
{}
|
|
};
|
|
|
|
static int nsp_gpio_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct nsp_gpio *chip;
|
|
struct gpio_chip *gc;
|
|
u32 val;
|
|
int irq, ret;
|
|
|
|
if (of_property_read_u32(pdev->dev.of_node, "ngpios", &val)) {
|
|
dev_err(&pdev->dev, "Missing ngpios OF property\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
|
|
if (!chip)
|
|
return -ENOMEM;
|
|
|
|
chip->dev = dev;
|
|
platform_set_drvdata(pdev, chip);
|
|
|
|
chip->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(chip->base)) {
|
|
dev_err(dev, "unable to map I/O memory\n");
|
|
return PTR_ERR(chip->base);
|
|
}
|
|
|
|
chip->io_ctrl = devm_platform_ioremap_resource(pdev, 1);
|
|
if (IS_ERR(chip->io_ctrl)) {
|
|
dev_err(dev, "unable to map I/O memory\n");
|
|
return PTR_ERR(chip->io_ctrl);
|
|
}
|
|
|
|
raw_spin_lock_init(&chip->lock);
|
|
gc = &chip->gc;
|
|
gc->base = -1;
|
|
gc->can_sleep = false;
|
|
gc->ngpio = val;
|
|
gc->label = dev_name(dev);
|
|
gc->parent = dev;
|
|
gc->of_node = dev->of_node;
|
|
gc->request = gpiochip_generic_request;
|
|
gc->free = gpiochip_generic_free;
|
|
gc->direction_input = nsp_gpio_direction_input;
|
|
gc->direction_output = nsp_gpio_direction_output;
|
|
gc->get_direction = nsp_gpio_get_direction;
|
|
gc->set = nsp_gpio_set;
|
|
gc->get = nsp_gpio_get;
|
|
|
|
/* optional GPIO interrupt support */
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq > 0) {
|
|
struct gpio_irq_chip *girq;
|
|
struct irq_chip *irqc;
|
|
|
|
irqc = &chip->irqchip;
|
|
irqc->name = "gpio-a";
|
|
irqc->irq_ack = nsp_gpio_irq_ack;
|
|
irqc->irq_mask = nsp_gpio_irq_mask;
|
|
irqc->irq_unmask = nsp_gpio_irq_unmask;
|
|
irqc->irq_set_type = nsp_gpio_irq_set_type;
|
|
|
|
val = readl(chip->base + NSP_CHIP_A_INT_MASK);
|
|
val = val | NSP_CHIP_A_GPIO_INT_BIT;
|
|
writel(val, (chip->base + NSP_CHIP_A_INT_MASK));
|
|
|
|
/* Install ISR for this GPIO controller. */
|
|
ret = devm_request_irq(dev, irq, nsp_gpio_irq_handler,
|
|
IRQF_SHARED, "gpio-a", &chip->gc);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n",
|
|
irq, ret);
|
|
return ret;
|
|
}
|
|
|
|
girq = &chip->gc.irq;
|
|
girq->chip = irqc;
|
|
/* This will let us handle the parent IRQ in the driver */
|
|
girq->parent_handler = NULL;
|
|
girq->num_parents = 0;
|
|
girq->parents = NULL;
|
|
girq->default_type = IRQ_TYPE_NONE;
|
|
girq->handler = handle_bad_irq;
|
|
}
|
|
|
|
ret = devm_gpiochip_add_data(dev, gc, chip);
|
|
if (ret < 0) {
|
|
dev_err(dev, "unable to add GPIO chip\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = nsp_gpio_register_pinconf(chip);
|
|
if (ret) {
|
|
dev_err(dev, "unable to register pinconf\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver nsp_gpio_driver = {
|
|
.driver = {
|
|
.name = "nsp-gpio-a",
|
|
.of_match_table = nsp_gpio_of_match,
|
|
},
|
|
.probe = nsp_gpio_probe,
|
|
};
|
|
|
|
static int __init nsp_gpio_init(void)
|
|
{
|
|
return platform_driver_register(&nsp_gpio_driver);
|
|
}
|
|
arch_initcall_sync(nsp_gpio_init);
|