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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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2d4dc890b5
Mtdblock driver doesn't call flush_dcache_page for pages in request. So, this causes problems on architectures where the icache doesn't fill from the dcache or with dcache aliases. The patch fixes this. The ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE symbol was introduced to avoid pointless empty cache-thrashing loops on architectures for which flush_dcache_page() is a no-op. Every architecture was provided with this flush pages on architectires where ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE is equal 1 or do nothing otherwise. See "fix mtd_blkdevs problem with caches on some architectures" discussion on LKML for more information. Signed-off-by: Ilya Loginov <isloginov@gmail.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Peter Horton <phorton@bitbox.co.uk> Cc: "Ed L. Cashin" <ecashin@coraid.com> Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
133 lines
3.9 KiB
C
133 lines
3.9 KiB
C
/*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_AVR32_CACHEFLUSH_H
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#define __ASM_AVR32_CACHEFLUSH_H
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/* Keep includes the same across arches. */
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#include <linux/mm.h>
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#define CACHE_OP_ICACHE_INVALIDATE 0x01
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#define CACHE_OP_DCACHE_INVALIDATE 0x0b
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#define CACHE_OP_DCACHE_CLEAN 0x0c
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#define CACHE_OP_DCACHE_CLEAN_INVAL 0x0d
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/*
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* Invalidate any cacheline containing virtual address vaddr without
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* writing anything back to memory.
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*
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* Note that this function may corrupt unrelated data structures when
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* applied on buffers that are not cacheline aligned in both ends.
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*/
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static inline void invalidate_dcache_line(void *vaddr)
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{
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asm volatile("cache %0[0], %1"
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:
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: "r"(vaddr), "n"(CACHE_OP_DCACHE_INVALIDATE)
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: "memory");
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}
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/*
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* Make sure any cacheline containing virtual address vaddr is written
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* to memory.
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*/
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static inline void clean_dcache_line(void *vaddr)
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{
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asm volatile("cache %0[0], %1"
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:
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: "r"(vaddr), "n"(CACHE_OP_DCACHE_CLEAN)
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: "memory");
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}
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/*
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* Make sure any cacheline containing virtual address vaddr is written
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* to memory and then invalidate it.
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*/
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static inline void flush_dcache_line(void *vaddr)
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{
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asm volatile("cache %0[0], %1"
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:
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: "r"(vaddr), "n"(CACHE_OP_DCACHE_CLEAN_INVAL)
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: "memory");
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}
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/*
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* Invalidate any instruction cacheline containing virtual address
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* vaddr.
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*/
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static inline void invalidate_icache_line(void *vaddr)
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{
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asm volatile("cache %0[0], %1"
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:
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: "r"(vaddr), "n"(CACHE_OP_ICACHE_INVALIDATE)
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: "memory");
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}
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/*
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* Applies the above functions on all lines that are touched by the
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* specified virtual address range.
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*/
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void invalidate_dcache_region(void *start, size_t len);
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void clean_dcache_region(void *start, size_t len);
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void flush_dcache_region(void *start, size_t len);
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void invalidate_icache_region(void *start, size_t len);
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/*
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* Make sure any pending writes are completed before continuing.
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*/
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#define flush_write_buffer() asm volatile("sync 0" : : : "memory")
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/*
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* The following functions are called when a virtual mapping changes.
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* We do not need to flush anything in this case.
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*/
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define flush_cache_vmap(start, end) do { } while (0)
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#define flush_cache_vunmap(start, end) do { } while (0)
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/*
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* I think we need to implement this one to be able to reliably
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* execute pages from RAMDISK. However, if we implement the
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* flush_dcache_*() functions, it might not be needed anymore.
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*
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* #define flush_icache_page(vma, page) do { } while (0)
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*/
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extern void flush_icache_page(struct vm_area_struct *vma, struct page *page);
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/*
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* These are (I think) related to D-cache aliasing. We might need to
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* do something here, but only for certain configurations. No such
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* configurations exist at this time.
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*/
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(page) do { } while (0)
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#define flush_dcache_mmap_unlock(page) do { } while (0)
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/*
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* These are for I/D cache coherency. In this case, we do need to
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* flush with all configurations.
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*/
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extern void flush_icache_range(unsigned long start, unsigned long end);
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extern void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
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unsigned long vaddr, void *dst, const void *src,
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unsigned long len);
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static inline void copy_from_user_page(struct vm_area_struct *vma,
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struct page *page, unsigned long vaddr, void *dst,
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const void *src, unsigned long len)
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{
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memcpy(dst, src, len);
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}
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#endif /* __ASM_AVR32_CACHEFLUSH_H */
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