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The devices from the ADAU17X1 family all have a MCLK clock input which supplies the master clock for the device. The master clock is used as the input clock for the PLL. Currently the MCLK rate as well as the desired PLL output frequency need to be supplied by calling snd_soc_dai_set_pll() form a machine driver. Add support for specifying the MCLK using the common clock framework. In addition to that also automatically configure the PLL to a suitable rate if the master clock was provided using the CCW. This allows to use the CODEC driver without any special configuration requirements from the machine driver. While the PLL output frequency can be configured over a (more or less) continuous range the narrowness of the range and the other constraints of the clocking tree usually only result in two output frequencies that will actually be chosen. One for 44.1kHz based rates and one for 48kHz based rates, these are the rates that the automatic PLL configuration will use. For the rare case where a non-standard setup is required a machine driver can disable the auto-configuration and configure a custom frequency using the existing mechanisms. If the common clock framework is not enabled clk_get() will return NULL and the driver will function as before and the clock rate needs to be configured manually. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@kernel.org>
33 lines
720 B
Plaintext
33 lines
720 B
Plaintext
Analog Devices ADAU1361/ADAU1461/ADAU1761/ADAU1961/ADAU1381/ADAU1781
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Required properties:
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- compatible: Should contain one of the following:
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"adi,adau1361"
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"adi,adau1461"
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"adi,adau1761"
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"adi,adau1961"
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"adi,adau1381"
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"adi,adau1781"
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- reg: The i2c address. Value depends on the state of ADDR0
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and ADDR1, as wired in hardware.
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Optional properties:
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- clock-names: If provided must be "mclk".
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- clocks: phandle + clock-specifiers for the clock that provides
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the audio master clock for the device.
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Examples:
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#include <dt-bindings/sound/adau17x1.h>
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i2c_bus {
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adau1361@38 {
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compatible = "adi,adau1761";
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reg = <0x38>;
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clock-names = "mclk";
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clocks = <&audio_clock>;
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};
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};
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