mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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308 lines
7.7 KiB
C
308 lines
7.7 KiB
C
/*
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* Driver for the TXx9 SoC DMA Controller
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*
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* Copyright (C) 2009 Atsushi Nemoto
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef TXX9DMAC_H
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#define TXX9DMAC_H
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#include <linux/dmaengine.h>
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#include <asm/txx9/dmac.h>
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/*
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* Design Notes:
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*
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* This DMAC have four channels and one FIFO buffer. Each channel can
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* be configured for memory-memory or device-memory transfer, but only
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* one channel can do alignment-free memory-memory transfer at a time
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* while the channel should occupy the FIFO buffer for effective
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* transfers.
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*
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* Instead of dynamically assign the FIFO buffer to channels, I chose
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* make one dedicated channel for memory-memory transfer. The
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* dedicated channel is public. Other channels are private and used
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* for slave transfer. Some devices in the SoC are wired to certain
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* DMA channel.
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*/
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#ifdef CONFIG_MACH_TX49XX
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static inline bool txx9_dma_have_SMPCHN(void)
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{
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return true;
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}
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#define TXX9_DMA_USE_SIMPLE_CHAIN
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#else
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static inline bool txx9_dma_have_SMPCHN(void)
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{
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return false;
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}
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#endif
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#ifdef __LITTLE_ENDIAN
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#ifdef CONFIG_MACH_TX49XX
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#define CCR_LE TXX9_DMA_CCR_LE
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#define MCR_LE 0
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#else
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#define CCR_LE 0
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#define MCR_LE TXX9_DMA_MCR_LE
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#endif
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#else
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#define CCR_LE 0
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#define MCR_LE 0
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#endif
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/*
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* Redefine this macro to handle differences between 32- and 64-bit
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* addressing, big vs. little endian, etc.
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*/
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#ifdef __BIG_ENDIAN
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#define TXX9_DMA_REG32(name) u32 __pad_##name; u32 name
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#else
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#define TXX9_DMA_REG32(name) u32 name; u32 __pad_##name
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#endif
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/* Hardware register definitions. */
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struct txx9dmac_cregs {
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#if defined(CONFIG_32BIT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
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TXX9_DMA_REG32(CHAR); /* Chain Address Register */
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#else
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u64 CHAR; /* Chain Address Register */
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#endif
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u64 SAR; /* Source Address Register */
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u64 DAR; /* Destination Address Register */
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TXX9_DMA_REG32(CNTR); /* Count Register */
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TXX9_DMA_REG32(SAIR); /* Source Address Increment Register */
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TXX9_DMA_REG32(DAIR); /* Destination Address Increment Register */
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TXX9_DMA_REG32(CCR); /* Channel Control Register */
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TXX9_DMA_REG32(CSR); /* Channel Status Register */
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};
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struct txx9dmac_cregs32 {
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u32 CHAR;
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u32 SAR;
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u32 DAR;
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u32 CNTR;
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u32 SAIR;
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u32 DAIR;
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u32 CCR;
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u32 CSR;
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};
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struct txx9dmac_regs {
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/* per-channel registers */
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struct txx9dmac_cregs CHAN[TXX9_DMA_MAX_NR_CHANNELS];
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u64 __pad[9];
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u64 MFDR; /* Memory Fill Data Register */
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TXX9_DMA_REG32(MCR); /* Master Control Register */
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};
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struct txx9dmac_regs32 {
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struct txx9dmac_cregs32 CHAN[TXX9_DMA_MAX_NR_CHANNELS];
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u32 __pad[9];
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u32 MFDR;
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u32 MCR;
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};
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/* bits for MCR */
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#define TXX9_DMA_MCR_EIS(ch) (0x10000000<<(ch))
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#define TXX9_DMA_MCR_DIS(ch) (0x01000000<<(ch))
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#define TXX9_DMA_MCR_RSFIF 0x00000080
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#define TXX9_DMA_MCR_FIFUM(ch) (0x00000008<<(ch))
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#define TXX9_DMA_MCR_LE 0x00000004
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#define TXX9_DMA_MCR_RPRT 0x00000002
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#define TXX9_DMA_MCR_MSTEN 0x00000001
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/* bits for CCRn */
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#define TXX9_DMA_CCR_IMMCHN 0x20000000
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#define TXX9_DMA_CCR_USEXFSZ 0x10000000
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#define TXX9_DMA_CCR_LE 0x08000000
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#define TXX9_DMA_CCR_DBINH 0x04000000
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#define TXX9_DMA_CCR_SBINH 0x02000000
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#define TXX9_DMA_CCR_CHRST 0x01000000
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#define TXX9_DMA_CCR_RVBYTE 0x00800000
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#define TXX9_DMA_CCR_ACKPOL 0x00400000
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#define TXX9_DMA_CCR_REQPL 0x00200000
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#define TXX9_DMA_CCR_EGREQ 0x00100000
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#define TXX9_DMA_CCR_CHDN 0x00080000
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#define TXX9_DMA_CCR_DNCTL 0x00060000
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#define TXX9_DMA_CCR_EXTRQ 0x00010000
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#define TXX9_DMA_CCR_INTRQD 0x0000e000
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#define TXX9_DMA_CCR_INTENE 0x00001000
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#define TXX9_DMA_CCR_INTENC 0x00000800
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#define TXX9_DMA_CCR_INTENT 0x00000400
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#define TXX9_DMA_CCR_CHNEN 0x00000200
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#define TXX9_DMA_CCR_XFACT 0x00000100
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#define TXX9_DMA_CCR_SMPCHN 0x00000020
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#define TXX9_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c)
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#define TXX9_DMA_CCR_XFSZ_1 TXX9_DMA_CCR_XFSZ(0)
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#define TXX9_DMA_CCR_XFSZ_2 TXX9_DMA_CCR_XFSZ(1)
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#define TXX9_DMA_CCR_XFSZ_4 TXX9_DMA_CCR_XFSZ(2)
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#define TXX9_DMA_CCR_XFSZ_8 TXX9_DMA_CCR_XFSZ(3)
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#define TXX9_DMA_CCR_XFSZ_X4 TXX9_DMA_CCR_XFSZ(4)
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#define TXX9_DMA_CCR_XFSZ_X8 TXX9_DMA_CCR_XFSZ(5)
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#define TXX9_DMA_CCR_XFSZ_X16 TXX9_DMA_CCR_XFSZ(6)
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#define TXX9_DMA_CCR_XFSZ_X32 TXX9_DMA_CCR_XFSZ(7)
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#define TXX9_DMA_CCR_MEMIO 0x00000002
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#define TXX9_DMA_CCR_SNGAD 0x00000001
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/* bits for CSRn */
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#define TXX9_DMA_CSR_CHNEN 0x00000400
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#define TXX9_DMA_CSR_STLXFER 0x00000200
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#define TXX9_DMA_CSR_XFACT 0x00000100
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#define TXX9_DMA_CSR_ABCHC 0x00000080
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#define TXX9_DMA_CSR_NCHNC 0x00000040
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#define TXX9_DMA_CSR_NTRNFC 0x00000020
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#define TXX9_DMA_CSR_EXTDN 0x00000010
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#define TXX9_DMA_CSR_CFERR 0x00000008
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#define TXX9_DMA_CSR_CHERR 0x00000004
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#define TXX9_DMA_CSR_DESERR 0x00000002
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#define TXX9_DMA_CSR_SORERR 0x00000001
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struct txx9dmac_chan {
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struct dma_chan chan;
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struct dma_device dma;
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struct txx9dmac_dev *ddev;
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void __iomem *ch_regs;
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struct tasklet_struct tasklet;
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int irq;
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u32 ccr;
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spinlock_t lock;
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/* these other elements are all protected by lock */
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struct list_head active_list;
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struct list_head queue;
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struct list_head free_list;
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unsigned int descs_allocated;
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};
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struct txx9dmac_dev {
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void __iomem *regs;
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struct tasklet_struct tasklet;
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int irq;
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struct txx9dmac_chan *chan[TXX9_DMA_MAX_NR_CHANNELS];
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bool have_64bit_regs;
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unsigned int descsize;
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};
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static inline bool __is_dmac64(const struct txx9dmac_dev *ddev)
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{
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return ddev->have_64bit_regs;
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}
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static inline bool is_dmac64(const struct txx9dmac_chan *dc)
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{
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return __is_dmac64(dc->ddev);
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}
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#ifdef TXX9_DMA_USE_SIMPLE_CHAIN
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/* Hardware descriptor definition. (for simple-chain) */
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struct txx9dmac_hwdesc {
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#if defined(CONFIG_32BIT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
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TXX9_DMA_REG32(CHAR);
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#else
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u64 CHAR;
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#endif
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u64 SAR;
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u64 DAR;
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TXX9_DMA_REG32(CNTR);
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};
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struct txx9dmac_hwdesc32 {
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u32 CHAR;
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u32 SAR;
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u32 DAR;
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u32 CNTR;
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};
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#else
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#define txx9dmac_hwdesc txx9dmac_cregs
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#define txx9dmac_hwdesc32 txx9dmac_cregs32
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#endif
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struct txx9dmac_desc {
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/* FIRST values the hardware uses */
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union {
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struct txx9dmac_hwdesc hwdesc;
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struct txx9dmac_hwdesc32 hwdesc32;
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};
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/* THEN values for driver housekeeping */
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struct list_head desc_node ____cacheline_aligned;
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struct list_head tx_list;
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struct dma_async_tx_descriptor txd;
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size_t len;
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};
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#ifdef TXX9_DMA_USE_SIMPLE_CHAIN
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static inline bool txx9dmac_chan_INTENT(struct txx9dmac_chan *dc)
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{
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return (dc->ccr & TXX9_DMA_CCR_INTENT) != 0;
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}
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static inline void txx9dmac_chan_set_INTENT(struct txx9dmac_chan *dc)
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{
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dc->ccr |= TXX9_DMA_CCR_INTENT;
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}
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static inline void txx9dmac_desc_set_INTENT(struct txx9dmac_dev *ddev,
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struct txx9dmac_desc *desc)
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{
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}
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static inline void txx9dmac_chan_set_SMPCHN(struct txx9dmac_chan *dc)
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{
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dc->ccr |= TXX9_DMA_CCR_SMPCHN;
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}
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static inline void txx9dmac_desc_set_nosimple(struct txx9dmac_dev *ddev,
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struct txx9dmac_desc *desc,
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u32 sair, u32 dair, u32 ccr)
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{
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}
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#else /* TXX9_DMA_USE_SIMPLE_CHAIN */
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static inline bool txx9dmac_chan_INTENT(struct txx9dmac_chan *dc)
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{
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return true;
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}
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static void txx9dmac_chan_set_INTENT(struct txx9dmac_chan *dc)
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{
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}
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static inline void txx9dmac_desc_set_INTENT(struct txx9dmac_dev *ddev,
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struct txx9dmac_desc *desc)
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{
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if (__is_dmac64(ddev))
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desc->hwdesc.CCR |= TXX9_DMA_CCR_INTENT;
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else
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desc->hwdesc32.CCR |= TXX9_DMA_CCR_INTENT;
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}
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static inline void txx9dmac_chan_set_SMPCHN(struct txx9dmac_chan *dc)
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{
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}
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static inline void txx9dmac_desc_set_nosimple(struct txx9dmac_dev *ddev,
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struct txx9dmac_desc *desc,
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u32 sai, u32 dai, u32 ccr)
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{
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if (__is_dmac64(ddev)) {
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desc->hwdesc.SAIR = sai;
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desc->hwdesc.DAIR = dai;
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desc->hwdesc.CCR = ccr;
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} else {
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desc->hwdesc32.SAIR = sai;
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desc->hwdesc32.DAIR = dai;
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desc->hwdesc32.CCR = ccr;
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}
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}
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#endif /* TXX9_DMA_USE_SIMPLE_CHAIN */
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#endif /* TXX9DMAC_H */
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