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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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64b61067de
AM43xx has a spinlock module which is identical to the one present on AM33xx. Register the spinlock ocp_if link so that the spinlock hwmod and associated omap_device can be instantiated, and the runtime pm API could be used by the OMAP hwspinlock driver. Cc: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
760 lines
19 KiB
C
760 lines
19 KiB
C
/*
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* Copyright (C) 2013 Texas Instruments Incorporated
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*
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* Hwmod present only in AM43x and those that differ other than register
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* offsets as compared to AM335x.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/platform_data/gpio-omap.h>
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#include <linux/platform_data/spi-omap2-mcspi.h>
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#include "omap_hwmod.h"
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#include "omap_hwmod_33xx_43xx_common_data.h"
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#include "prcm43xx.h"
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/* IP blocks */
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static struct omap_hwmod am43xx_l4_hs_hwmod = {
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.name = "l4_hs",
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.class = &am33xx_l4_hwmod_class,
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.clkdm_name = "l3_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "l4hs_gclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
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{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
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};
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static struct omap_hwmod am43xx_wkup_m3_hwmod = {
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.name = "wkup_m3",
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.class = &am33xx_wkup_m3_hwmod_class,
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.clkdm_name = "l4_wkup_aon_clkdm",
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/* Keep hardreset asserted */
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.flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
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.main_clk = "sys_clkin_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
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.rstctrl_offs = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
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.rstst_offs = AM43XX_RM_WKUP_RSTST_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.rst_lines = am33xx_wkup_m3_resets,
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.rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
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};
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static struct omap_hwmod am43xx_control_hwmod = {
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.name = "control",
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.class = &am33xx_control_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "sys_clkin_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
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{ .role = "dbclk", .clk = "gpio0_dbclk" },
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};
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static struct omap_hwmod am43xx_gpio0_hwmod = {
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.name = "gpio1",
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.class = &am33xx_gpio_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.main_clk = "sys_clkin_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.opt_clks = gpio0_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
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.dev_attr = &gpio_dev_attr,
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};
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static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
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.rev_offs = 0x0,
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.sysc_offs = 0x4,
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.sysc_flags = SYSC_HAS_SIDLEMODE,
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.idlemodes = (SIDLE_FORCE | SIDLE_NO),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
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.name = "synctimer",
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.sysc = &am43xx_synctimer_sysc,
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};
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static struct omap_hwmod am43xx_synctimer_hwmod = {
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.name = "counter_32k",
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.class = &am43xx_synctimer_hwmod_class,
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.clkdm_name = "l4_wkup_aon_clkdm",
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.flags = HWMOD_SWSUP_SIDLE,
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.main_clk = "synctimer_32kclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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static struct omap_hwmod am43xx_timer8_hwmod = {
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.name = "timer8",
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.class = &am33xx_timer_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "timer8_fck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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static struct omap_hwmod am43xx_timer9_hwmod = {
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.name = "timer9",
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.class = &am33xx_timer_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "timer9_fck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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static struct omap_hwmod am43xx_timer10_hwmod = {
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.name = "timer10",
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.class = &am33xx_timer_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "timer10_fck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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static struct omap_hwmod am43xx_timer11_hwmod = {
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.name = "timer11",
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.class = &am33xx_timer_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "timer11_fck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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static struct omap_hwmod am43xx_epwmss3_hwmod = {
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.name = "epwmss3",
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.class = &am33xx_epwmss_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "l4ls_gclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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static struct omap_hwmod am43xx_ehrpwm3_hwmod = {
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.name = "ehrpwm3",
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.class = &am33xx_ehrpwm_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "l4ls_gclk",
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};
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static struct omap_hwmod am43xx_epwmss4_hwmod = {
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.name = "epwmss4",
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.class = &am33xx_epwmss_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "l4ls_gclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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static struct omap_hwmod am43xx_ehrpwm4_hwmod = {
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.name = "ehrpwm4",
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.class = &am33xx_ehrpwm_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "l4ls_gclk",
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};
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static struct omap_hwmod am43xx_epwmss5_hwmod = {
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.name = "epwmss5",
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.class = &am33xx_epwmss_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "l4ls_gclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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static struct omap_hwmod am43xx_ehrpwm5_hwmod = {
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.name = "ehrpwm5",
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.class = &am33xx_ehrpwm_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "l4ls_gclk",
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};
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static struct omap_hwmod am43xx_spi2_hwmod = {
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.name = "spi2",
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.class = &am33xx_spi_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "dpll_per_m2_div4_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.dev_attr = &mcspi_attrib,
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};
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static struct omap_hwmod am43xx_spi3_hwmod = {
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.name = "spi3",
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.class = &am33xx_spi_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "dpll_per_m2_div4_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.dev_attr = &mcspi_attrib,
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};
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static struct omap_hwmod am43xx_spi4_hwmod = {
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.name = "spi4",
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.class = &am33xx_spi_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "dpll_per_m2_div4_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.dev_attr = &mcspi_attrib,
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};
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static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
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{ .role = "dbclk", .clk = "gpio4_dbclk" },
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};
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static struct omap_hwmod am43xx_gpio4_hwmod = {
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.name = "gpio5",
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.class = &am33xx_gpio_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.main_clk = "l4ls_gclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.opt_clks = gpio4_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
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.dev_attr = &gpio_dev_attr,
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};
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static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
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{ .role = "dbclk", .clk = "gpio5_dbclk" },
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};
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static struct omap_hwmod am43xx_gpio5_hwmod = {
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.name = "gpio6",
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.class = &am33xx_gpio_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.main_clk = "l4ls_gclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.opt_clks = gpio5_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
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.dev_attr = &gpio_dev_attr,
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};
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static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
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.name = "ocp2scp",
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};
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static struct omap_hwmod am43xx_ocp2scp0_hwmod = {
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.name = "ocp2scp0",
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.class = &am43xx_ocp2scp_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "l4ls_gclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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static struct omap_hwmod am43xx_ocp2scp1_hwmod = {
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.name = "ocp2scp1",
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.class = &am43xx_ocp2scp_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "l4ls_gclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
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SYSC_HAS_SIDLEMODE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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SIDLE_SMART_WKUP | MSTANDBY_FORCE |
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MSTANDBY_NO | MSTANDBY_SMART |
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MSTANDBY_SMART_WKUP),
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.sysc_fields = &omap_hwmod_sysc_type2,
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};
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static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
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.name = "usb_otg_ss",
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.sysc = &am43xx_usb_otg_ss_sysc,
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};
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static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
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.name = "usb_otg_ss0",
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.class = &am43xx_usb_otg_ss_hwmod_class,
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.clkdm_name = "l3s_clkdm",
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.main_clk = "l3s_gclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
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.name = "usb_otg_ss1",
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.class = &am43xx_usb_otg_ss_hwmod_class,
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.clkdm_name = "l3s_clkdm",
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.main_clk = "l3s_gclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = {
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.sysc_offs = 0x0010,
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.sysc_flags = SYSC_HAS_SIDLEMODE,
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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SIDLE_SMART_WKUP),
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.sysc_fields = &omap_hwmod_sysc_type2,
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};
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static struct omap_hwmod_class am43xx_qspi_hwmod_class = {
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.name = "qspi",
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.sysc = &am43xx_qspi_sysc,
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};
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static struct omap_hwmod am43xx_qspi_hwmod = {
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.name = "qspi",
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.class = &am43xx_qspi_hwmod_class,
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.clkdm_name = "l3s_clkdm",
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.main_clk = "l3s_gclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* Interfaces */
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static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
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.master = &am33xx_l3_main_hwmod,
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.slave = &am43xx_l4_hs_hwmod,
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.clk = "l3s_gclk",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
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.master = &am43xx_wkup_m3_hwmod,
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.slave = &am33xx_l4_wkup_hwmod,
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.clk = "sys_clkin_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
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.master = &am33xx_l4_wkup_hwmod,
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.slave = &am43xx_wkup_m3_hwmod,
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.clk = "sys_clkin_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
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.master = &am33xx_l3_main_hwmod,
|
|
.slave = &am33xx_pruss_hwmod,
|
|
.clk = "dpll_core_m4_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
|
|
.master = &am33xx_l4_wkup_hwmod,
|
|
.slave = &am33xx_smartreflex0_hwmod,
|
|
.clk = "sys_clkin_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
|
|
.master = &am33xx_l4_wkup_hwmod,
|
|
.slave = &am33xx_smartreflex1_hwmod,
|
|
.clk = "sys_clkin_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
|
|
.master = &am33xx_l4_wkup_hwmod,
|
|
.slave = &am43xx_control_hwmod,
|
|
.clk = "sys_clkin_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = {
|
|
.master = &am33xx_l4_wkup_hwmod,
|
|
.slave = &am33xx_i2c1_hwmod,
|
|
.clk = "sys_clkin_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
|
|
.master = &am33xx_l4_wkup_hwmod,
|
|
.slave = &am43xx_gpio0_hwmod,
|
|
.clk = "sys_clkin_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
|
|
.master = &am43xx_l4_hs_hwmod,
|
|
.slave = &am33xx_cpgmac0_hwmod,
|
|
.clk = "cpsw_125mhz_gclk",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
|
|
.master = &am33xx_l4_wkup_hwmod,
|
|
.slave = &am33xx_timer1_hwmod,
|
|
.clk = "sys_clkin_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = {
|
|
.master = &am33xx_l4_wkup_hwmod,
|
|
.slave = &am33xx_uart1_hwmod,
|
|
.clk = "sys_clkin_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
|
|
.master = &am33xx_l4_wkup_hwmod,
|
|
.slave = &am33xx_wd_timer1_hwmod,
|
|
.clk = "sys_clkin_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
|
|
.master = &am33xx_l4_wkup_hwmod,
|
|
.slave = &am43xx_synctimer_hwmod,
|
|
.clk = "sys_clkin_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
|
|
.master = &am33xx_l4_ls_hwmod,
|
|
.slave = &am43xx_timer8_hwmod,
|
|
.clk = "l4ls_gclk",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
|
|
.master = &am33xx_l4_ls_hwmod,
|
|
.slave = &am43xx_timer9_hwmod,
|
|
.clk = "l4ls_gclk",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
|
|
.master = &am33xx_l4_ls_hwmod,
|
|
.slave = &am43xx_timer10_hwmod,
|
|
.clk = "l4ls_gclk",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
|
|
.master = &am33xx_l4_ls_hwmod,
|
|
.slave = &am43xx_timer11_hwmod,
|
|
.clk = "l4ls_gclk",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
|
|
.master = &am33xx_l4_ls_hwmod,
|
|
.slave = &am43xx_epwmss3_hwmod,
|
|
.clk = "l4ls_gclk",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = {
|
|
.master = &am43xx_epwmss3_hwmod,
|
|
.slave = &am43xx_ehrpwm3_hwmod,
|
|
.clk = "l4ls_gclk",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
|
|
.master = &am33xx_l4_ls_hwmod,
|
|
.slave = &am43xx_epwmss4_hwmod,
|
|
.clk = "l4ls_gclk",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = {
|
|
.master = &am43xx_epwmss4_hwmod,
|
|
.slave = &am43xx_ehrpwm4_hwmod,
|
|
.clk = "l4ls_gclk",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
|
|
.master = &am33xx_l4_ls_hwmod,
|
|
.slave = &am43xx_epwmss5_hwmod,
|
|
.clk = "l4ls_gclk",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = {
|
|
.master = &am43xx_epwmss5_hwmod,
|
|
.slave = &am43xx_ehrpwm5_hwmod,
|
|
.clk = "l4ls_gclk",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
|
|
.master = &am33xx_l4_ls_hwmod,
|
|
.slave = &am43xx_spi2_hwmod,
|
|
.clk = "l4ls_gclk",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
|
|
.master = &am33xx_l4_ls_hwmod,
|
|
.slave = &am43xx_spi3_hwmod,
|
|
.clk = "l4ls_gclk",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
|
|
.master = &am33xx_l4_ls_hwmod,
|
|
.slave = &am43xx_spi4_hwmod,
|
|
.clk = "l4ls_gclk",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
|
|
.master = &am33xx_l4_ls_hwmod,
|
|
.slave = &am43xx_gpio4_hwmod,
|
|
.clk = "l4ls_gclk",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
|
|
.master = &am33xx_l4_ls_hwmod,
|
|
.slave = &am43xx_gpio5_hwmod,
|
|
.clk = "l4ls_gclk",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
|
|
.master = &am33xx_l4_ls_hwmod,
|
|
.slave = &am43xx_ocp2scp0_hwmod,
|
|
.clk = "l4ls_gclk",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = {
|
|
.master = &am33xx_l4_ls_hwmod,
|
|
.slave = &am43xx_ocp2scp1_hwmod,
|
|
.clk = "l4ls_gclk",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
|
|
.master = &am33xx_l3_s_hwmod,
|
|
.slave = &am43xx_usb_otg_ss0_hwmod,
|
|
.clk = "l3s_gclk",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
|
|
.master = &am33xx_l3_s_hwmod,
|
|
.slave = &am43xx_usb_otg_ss1_hwmod,
|
|
.clk = "l3s_gclk",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
|
|
.master = &am33xx_l3_s_hwmod,
|
|
.slave = &am43xx_qspi_hwmod,
|
|
.clk = "l3s_gclk",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
|
|
&am33xx_l4_wkup__synctimer,
|
|
&am43xx_l4_ls__timer8,
|
|
&am43xx_l4_ls__timer9,
|
|
&am43xx_l4_ls__timer10,
|
|
&am43xx_l4_ls__timer11,
|
|
&am43xx_l4_ls__epwmss3,
|
|
&am43xx_epwmss3__ehrpwm3,
|
|
&am43xx_l4_ls__epwmss4,
|
|
&am43xx_epwmss4__ehrpwm4,
|
|
&am43xx_l4_ls__epwmss5,
|
|
&am43xx_epwmss5__ehrpwm5,
|
|
&am43xx_l4_ls__mcspi2,
|
|
&am43xx_l4_ls__mcspi3,
|
|
&am43xx_l4_ls__mcspi4,
|
|
&am43xx_l4_ls__gpio4,
|
|
&am43xx_l4_ls__gpio5,
|
|
&am43xx_l3_main__pruss,
|
|
&am33xx_mpu__l3_main,
|
|
&am33xx_mpu__prcm,
|
|
&am33xx_l3_s__l4_ls,
|
|
&am33xx_l3_s__l4_wkup,
|
|
&am43xx_l3_main__l4_hs,
|
|
&am33xx_l3_main__l3_s,
|
|
&am33xx_l3_main__l3_instr,
|
|
&am33xx_l3_main__gfx,
|
|
&am33xx_l3_s__l3_main,
|
|
&am33xx_pruss__l3_main,
|
|
&am43xx_wkup_m3__l4_wkup,
|
|
&am33xx_gfx__l3_main,
|
|
&am43xx_l4_wkup__wkup_m3,
|
|
&am43xx_l4_wkup__control,
|
|
&am43xx_l4_wkup__smartreflex0,
|
|
&am43xx_l4_wkup__smartreflex1,
|
|
&am43xx_l4_wkup__uart1,
|
|
&am43xx_l4_wkup__timer1,
|
|
&am43xx_l4_wkup__i2c1,
|
|
&am43xx_l4_wkup__gpio0,
|
|
&am43xx_l4_wkup__wd_timer1,
|
|
&am43xx_l3_s__qspi,
|
|
&am33xx_l4_per__dcan0,
|
|
&am33xx_l4_per__dcan1,
|
|
&am33xx_l4_per__gpio1,
|
|
&am33xx_l4_per__gpio2,
|
|
&am33xx_l4_per__gpio3,
|
|
&am33xx_l4_per__i2c2,
|
|
&am33xx_l4_per__i2c3,
|
|
&am33xx_l4_per__mailbox,
|
|
&am33xx_l4_ls__mcasp0,
|
|
&am33xx_l4_ls__mcasp1,
|
|
&am33xx_l4_ls__mmc0,
|
|
&am33xx_l4_ls__mmc1,
|
|
&am33xx_l3_s__mmc2,
|
|
&am33xx_l4_ls__timer2,
|
|
&am33xx_l4_ls__timer3,
|
|
&am33xx_l4_ls__timer4,
|
|
&am33xx_l4_ls__timer5,
|
|
&am33xx_l4_ls__timer6,
|
|
&am33xx_l4_ls__timer7,
|
|
&am33xx_l3_main__tpcc,
|
|
&am33xx_l4_ls__uart2,
|
|
&am33xx_l4_ls__uart3,
|
|
&am33xx_l4_ls__uart4,
|
|
&am33xx_l4_ls__uart5,
|
|
&am33xx_l4_ls__uart6,
|
|
&am33xx_l4_ls__spinlock,
|
|
&am33xx_l4_ls__elm,
|
|
&am33xx_l4_ls__epwmss0,
|
|
&am33xx_epwmss0__ecap0,
|
|
&am33xx_epwmss0__eqep0,
|
|
&am33xx_epwmss0__ehrpwm0,
|
|
&am33xx_l4_ls__epwmss1,
|
|
&am33xx_epwmss1__ecap1,
|
|
&am33xx_epwmss1__eqep1,
|
|
&am33xx_epwmss1__ehrpwm1,
|
|
&am33xx_l4_ls__epwmss2,
|
|
&am33xx_epwmss2__ecap2,
|
|
&am33xx_epwmss2__eqep2,
|
|
&am33xx_epwmss2__ehrpwm2,
|
|
&am33xx_l3_s__gpmc,
|
|
&am33xx_l4_ls__mcspi0,
|
|
&am33xx_l4_ls__mcspi1,
|
|
&am33xx_l3_main__tptc0,
|
|
&am33xx_l3_main__tptc1,
|
|
&am33xx_l3_main__tptc2,
|
|
&am33xx_l3_main__ocmc,
|
|
&am43xx_l4_hs__cpgmac0,
|
|
&am33xx_cpgmac0__mdio,
|
|
&am33xx_l3_main__sha0,
|
|
&am33xx_l3_main__aes0,
|
|
&am43xx_l4_ls__ocp2scp0,
|
|
&am43xx_l4_ls__ocp2scp1,
|
|
&am43xx_l3_s__usbotgss0,
|
|
&am43xx_l3_s__usbotgss1,
|
|
NULL,
|
|
};
|
|
|
|
int __init am43xx_hwmod_init(void)
|
|
{
|
|
omap_hwmod_am43xx_reg();
|
|
omap_hwmod_init();
|
|
return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
|
|
}
|