Nadav Amit c4e8fa21a3 iommu/vt-d: Do not use flush-queue when caching-mode is on ... commit 29b32839725f8c89a41cb6ee054c85f3116ea8b5 upstream. When an Intel IOMMU is virtualized, and a physical device is passed-through to the VM, changes of the virtual IOMMU need to be propagated to the physical IOMMU. The hypervisor therefore needs to monitor PTE mappings in the IOMMU page-tables. Intel specifications provide "caching-mode" capability that a virtual IOMMU uses to report that the IOMMU is virtualized and a TLB flush is needed after mapping to allow the hypervisor to propagate virtual IOMMU mappings to the physical IOMMU. To the best of my knowledge no real physical IOMMU reports "caching-mode" as turned on. Synchronizing the virtual and the physical IOMMU tables is expensive if the hypervisor is unaware which PTEs have changed, as the hypervisor is required to walk all the virtualized tables and look for changes. Consequently, domain flushes are much more expensive than page-specific flushes on virtualized IOMMUs with passthrough devices. The kernel therefore exploited the "caching-mode" indication to avoid domain flushing and use page-specific flushing in virtualized environments. See commit 78d5f0f500 ("intel-iommu: Avoid global flushes with caching mode.") This behavior changed after commit 13cf017446 ("iommu/vt-d: Make use of iova deferred flushing"). Now, when batched TLB flushing is used (the default), full TLB domain flushes are performed frequently, requiring the hypervisor to perform expensive synchronization between the virtual TLB and the physical one. Getting batched TLB flushes to use page-specific invalidations again in such circumstances is not easy, since the TLB invalidation scheme assumes that "full" domain TLB flushes are performed for scalability. Disable batched TLB flushes when caching-mode is on, as the performance benefit from using batched TLB invalidations is likely to be much smaller than the overhead of the virtual-to-physical IOMMU page-tables synchronization. Fixes: 13cf017446 ("iommu/vt-d: Make use of iova deferred flushing") Signed-off-by: Nadav Amit <namit@vmware.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Lu Baolu <baolu.lu@linux.intel.com> Cc: Joerg Roedel <joro@8bytes.org> Cc: Will Deacon <will@kernel.org> Cc: stable@vger.kernel.org Acked-by: Lu Baolu <baolu.lu@linux.intel.com> Link: https://lore.kernel.org/r/20210127175317.1600473-1-namit@vmware.com Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2021-02-07 15:37:13 +01:00
..
amd
arm
intel	iommu/vt-d: Do not use flush-queue when caching-mode is on	2021-02-07 15:37:13 +01:00
dma-iommu.c
exynos-iommu.c
fsl_pamu_domain.c
fsl_pamu_domain.h
fsl_pamu.c
fsl_pamu.h
hyperv-iommu.c
io-pgtable-arm-v7s.c
io-pgtable-arm.c	iommu/io-pgtable-arm: Support coherency for Mali LPAE	2021-02-07 15:37:12 +01:00
io-pgtable-arm.h
io-pgtable.c
ioasid.c
iommu-debugfs.c
iommu-sysfs.c
iommu-traces.c
iommu.c
iova.c
ipmmu-vmsa.c
irq_remapping.c
irq_remapping.h
Kconfig
Makefile
msm_iommu_hw-8xxx.h
msm_iommu.c
msm_iommu.h
mtk_iommu_v1.c
mtk_iommu.c
mtk_iommu.h
of_iommu.c
omap-iommu-debug.c
omap-iommu.c
omap-iommu.h
omap-iopgtable.h
rockchip-iommu.c
s390-iommu.c
sun50i-iommu.c
tegra-gart.c
tegra-smmu.c
virtio-iommu.c