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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 21:55:41 +07:00
27777890d0
When building with CRYPTO_SHA1_PPC enabled we fail with:
powerpc/crypto/sha1-powerpc-asm.S: Assembler messages:
powerpc/crypto/sha1-powerpc-asm.S:116: Error: can't resolve `0' {*ABS* section} - `STACKFRAMESIZE' {*UND* section}
powerpc/crypto/sha1-powerpc-asm.S:116: Error: expression too complex
powerpc/crypto/sha1-powerpc-asm.S:178: Error: unsupported relocation against STACKFRAMESIZE
Use INT_FRAME_SIZE instead of STACKFRAMESIZE.
Signed-off-by: Tony Breeds <tony@bakeyournoodle.com>
Tested-by: Christian Kujau <lists@nerdbynature.de>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
180 lines
3.7 KiB
ArmAsm
180 lines
3.7 KiB
ArmAsm
/*
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* SHA-1 implementation for PowerPC.
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*
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* Copyright (C) 2005 Paul Mackerras <paulus@samba.org>
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*/
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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/*
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* We roll the registers for T, A, B, C, D, E around on each
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* iteration; T on iteration t is A on iteration t+1, and so on.
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* We use registers 7 - 12 for this.
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*/
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#define RT(t) ((((t)+5)%6)+7)
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#define RA(t) ((((t)+4)%6)+7)
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#define RB(t) ((((t)+3)%6)+7)
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#define RC(t) ((((t)+2)%6)+7)
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#define RD(t) ((((t)+1)%6)+7)
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#define RE(t) ((((t)+0)%6)+7)
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/* We use registers 16 - 31 for the W values */
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#define W(t) (((t)%16)+16)
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#define LOADW(t) \
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lwz W(t),(t)*4(r4)
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#define STEPD0_LOAD(t) \
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andc r0,RD(t),RB(t); \
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and r6,RB(t),RC(t); \
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rotlwi RT(t),RA(t),5; \
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or r6,r6,r0; \
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add r0,RE(t),r15; \
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add RT(t),RT(t),r6; \
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add r14,r0,W(t); \
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lwz W((t)+4),((t)+4)*4(r4); \
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rotlwi RB(t),RB(t),30; \
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add RT(t),RT(t),r14
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#define STEPD0_UPDATE(t) \
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and r6,RB(t),RC(t); \
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andc r0,RD(t),RB(t); \
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rotlwi RT(t),RA(t),5; \
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rotlwi RB(t),RB(t),30; \
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or r6,r6,r0; \
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add r0,RE(t),r15; \
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xor r5,W((t)+4-3),W((t)+4-8); \
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add RT(t),RT(t),r6; \
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xor W((t)+4),W((t)+4-16),W((t)+4-14); \
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add r0,r0,W(t); \
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xor W((t)+4),W((t)+4),r5; \
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add RT(t),RT(t),r0; \
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rotlwi W((t)+4),W((t)+4),1
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#define STEPD1(t) \
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xor r6,RB(t),RC(t); \
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rotlwi RT(t),RA(t),5; \
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rotlwi RB(t),RB(t),30; \
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xor r6,r6,RD(t); \
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add r0,RE(t),r15; \
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add RT(t),RT(t),r6; \
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add r0,r0,W(t); \
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add RT(t),RT(t),r0
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#define STEPD1_UPDATE(t) \
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xor r6,RB(t),RC(t); \
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rotlwi RT(t),RA(t),5; \
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rotlwi RB(t),RB(t),30; \
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xor r6,r6,RD(t); \
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add r0,RE(t),r15; \
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xor r5,W((t)+4-3),W((t)+4-8); \
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add RT(t),RT(t),r6; \
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xor W((t)+4),W((t)+4-16),W((t)+4-14); \
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add r0,r0,W(t); \
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xor W((t)+4),W((t)+4),r5; \
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add RT(t),RT(t),r0; \
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rotlwi W((t)+4),W((t)+4),1
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#define STEPD2_UPDATE(t) \
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and r6,RB(t),RC(t); \
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and r0,RB(t),RD(t); \
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rotlwi RT(t),RA(t),5; \
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or r6,r6,r0; \
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rotlwi RB(t),RB(t),30; \
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and r0,RC(t),RD(t); \
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xor r5,W((t)+4-3),W((t)+4-8); \
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or r6,r6,r0; \
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xor W((t)+4),W((t)+4-16),W((t)+4-14); \
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add r0,RE(t),r15; \
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add RT(t),RT(t),r6; \
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add r0,r0,W(t); \
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xor W((t)+4),W((t)+4),r5; \
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add RT(t),RT(t),r0; \
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rotlwi W((t)+4),W((t)+4),1
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#define STEP0LD4(t) \
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STEPD0_LOAD(t); \
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STEPD0_LOAD((t)+1); \
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STEPD0_LOAD((t)+2); \
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STEPD0_LOAD((t)+3)
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#define STEPUP4(t, fn) \
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STEP##fn##_UPDATE(t); \
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STEP##fn##_UPDATE((t)+1); \
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STEP##fn##_UPDATE((t)+2); \
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STEP##fn##_UPDATE((t)+3)
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#define STEPUP20(t, fn) \
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STEPUP4(t, fn); \
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STEPUP4((t)+4, fn); \
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STEPUP4((t)+8, fn); \
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STEPUP4((t)+12, fn); \
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STEPUP4((t)+16, fn)
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_GLOBAL(powerpc_sha_transform)
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PPC_STLU r1,-INT_FRAME_SIZE(r1)
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SAVE_8GPRS(14, r1)
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SAVE_10GPRS(22, r1)
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/* Load up A - E */
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lwz RA(0),0(r3) /* A */
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lwz RB(0),4(r3) /* B */
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lwz RC(0),8(r3) /* C */
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lwz RD(0),12(r3) /* D */
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lwz RE(0),16(r3) /* E */
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LOADW(0)
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LOADW(1)
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LOADW(2)
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LOADW(3)
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lis r15,0x5a82 /* K0-19 */
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ori r15,r15,0x7999
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STEP0LD4(0)
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STEP0LD4(4)
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STEP0LD4(8)
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STEPUP4(12, D0)
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STEPUP4(16, D0)
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lis r15,0x6ed9 /* K20-39 */
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ori r15,r15,0xeba1
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STEPUP20(20, D1)
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lis r15,0x8f1b /* K40-59 */
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ori r15,r15,0xbcdc
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STEPUP20(40, D2)
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lis r15,0xca62 /* K60-79 */
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ori r15,r15,0xc1d6
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STEPUP4(60, D1)
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STEPUP4(64, D1)
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STEPUP4(68, D1)
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STEPUP4(72, D1)
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lwz r20,16(r3)
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STEPD1(76)
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lwz r19,12(r3)
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STEPD1(77)
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lwz r18,8(r3)
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STEPD1(78)
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lwz r17,4(r3)
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STEPD1(79)
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lwz r16,0(r3)
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add r20,RE(80),r20
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add RD(0),RD(80),r19
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add RC(0),RC(80),r18
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add RB(0),RB(80),r17
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add RA(0),RA(80),r16
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mr RE(0),r20
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stw RA(0),0(r3)
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stw RB(0),4(r3)
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stw RC(0),8(r3)
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stw RD(0),12(r3)
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stw RE(0),16(r3)
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REST_8GPRS(14, r1)
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REST_10GPRS(22, r1)
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addi r1,r1,INT_FRAME_SIZE
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blr
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