mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 00:46:47 +07:00
231 lines
6.0 KiB
C
231 lines
6.0 KiB
C
/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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int
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nvc0_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj,
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u32 *size, u32 align)
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{
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int ret;
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*size = ALIGN(*size, 4096);
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if (*size == 0)
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return -EINVAL;
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ret = nouveau_bo_new(dev, NULL, *size, align, TTM_PL_FLAG_VRAM,
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0, 0x0000, true, false, &gpuobj->im_backing);
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if (ret) {
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NV_ERROR(dev, "error getting PRAMIN backing pages: %d\n", ret);
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return ret;
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}
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ret = nouveau_bo_pin(gpuobj->im_backing, TTM_PL_FLAG_VRAM);
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if (ret) {
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NV_ERROR(dev, "error pinning PRAMIN backing VRAM: %d\n", ret);
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nouveau_bo_ref(NULL, &gpuobj->im_backing);
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return ret;
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}
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gpuobj->vinst = gpuobj->im_backing->bo.mem.start << PAGE_SHIFT;
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return 0;
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}
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void
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nvc0_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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if (gpuobj && gpuobj->im_backing) {
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if (gpuobj->im_bound)
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dev_priv->engine.instmem.unbind(dev, gpuobj);
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nouveau_bo_unpin(gpuobj->im_backing);
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nouveau_bo_ref(NULL, &gpuobj->im_backing);
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gpuobj->im_backing = NULL;
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}
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}
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int
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nvc0_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t pte, pte_end;
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uint64_t vram;
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if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound)
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return -EINVAL;
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NV_DEBUG(dev, "st=0x%lx sz=0x%lx\n",
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gpuobj->im_pramin->start, gpuobj->im_pramin->size);
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pte = gpuobj->im_pramin->start >> 12;
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pte_end = (gpuobj->im_pramin->size >> 12) + pte;
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vram = gpuobj->vinst;
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NV_DEBUG(dev, "pramin=0x%lx, pte=%d, pte_end=%d\n",
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gpuobj->im_pramin->start, pte, pte_end);
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NV_DEBUG(dev, "first vram page: 0x%010llx\n", gpuobj->vinst);
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while (pte < pte_end) {
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nv_wr32(dev, 0x702000 + (pte * 8), (vram >> 8) | 1);
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nv_wr32(dev, 0x702004 + (pte * 8), 0);
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vram += 4096;
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pte++;
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}
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dev_priv->engine.instmem.flush(dev);
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if (1) {
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u32 chan = nv_rd32(dev, 0x1700) << 16;
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nv_wr32(dev, 0x100cb8, (chan + 0x1000) >> 8);
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nv_wr32(dev, 0x100cbc, 0x80000005);
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}
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gpuobj->im_bound = 1;
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return 0;
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}
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int
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nvc0_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t pte, pte_end;
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if (gpuobj->im_bound == 0)
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return -EINVAL;
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pte = gpuobj->im_pramin->start >> 12;
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pte_end = (gpuobj->im_pramin->size >> 12) + pte;
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while (pte < pte_end) {
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nv_wr32(dev, 0x702000 + (pte * 8), 0);
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nv_wr32(dev, 0x702004 + (pte * 8), 0);
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pte++;
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}
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dev_priv->engine.instmem.flush(dev);
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gpuobj->im_bound = 0;
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return 0;
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}
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void
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nvc0_instmem_flush(struct drm_device *dev)
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{
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nv_wr32(dev, 0x070000, 1);
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if (!nv_wait(dev, 0x070000, 0x00000002, 0x00000000))
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NV_ERROR(dev, "PRAMIN flush timeout\n");
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}
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int
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nvc0_instmem_suspend(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 *buf;
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int i;
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dev_priv->susres.ramin_copy = vmalloc(65536);
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if (!dev_priv->susres.ramin_copy)
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return -ENOMEM;
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buf = dev_priv->susres.ramin_copy;
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for (i = 0; i < 65536; i += 4)
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buf[i/4] = nv_rd32(dev, NV04_PRAMIN + i);
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return 0;
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}
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void
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nvc0_instmem_resume(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 *buf = dev_priv->susres.ramin_copy;
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u64 chan;
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int i;
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chan = dev_priv->vram_size - dev_priv->ramin_rsvd_vram;
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nv_wr32(dev, 0x001700, chan >> 16);
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for (i = 0; i < 65536; i += 4)
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nv_wr32(dev, NV04_PRAMIN + i, buf[i/4]);
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vfree(dev_priv->susres.ramin_copy);
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dev_priv->susres.ramin_copy = NULL;
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nv_wr32(dev, 0x001714, 0xc0000000 | (chan >> 12));
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}
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int
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nvc0_instmem_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u64 chan, pgt3, imem, lim3 = dev_priv->ramin_size - 1;
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int ret, i;
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dev_priv->ramin_rsvd_vram = 1 * 1024 * 1024;
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chan = dev_priv->vram_size - dev_priv->ramin_rsvd_vram;
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imem = 4096 + 4096 + 32768;
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nv_wr32(dev, 0x001700, chan >> 16);
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/* channel setup */
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nv_wr32(dev, 0x700200, lower_32_bits(chan + 0x1000));
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nv_wr32(dev, 0x700204, upper_32_bits(chan + 0x1000));
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nv_wr32(dev, 0x700208, lower_32_bits(lim3));
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nv_wr32(dev, 0x70020c, upper_32_bits(lim3));
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/* point pgd -> pgt */
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nv_wr32(dev, 0x701000, 0);
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nv_wr32(dev, 0x701004, ((chan + 0x2000) >> 8) | 1);
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/* point pgt -> physical vram for channel */
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pgt3 = 0x2000;
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for (i = 0; i < dev_priv->ramin_rsvd_vram; i += 4096, pgt3 += 8) {
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nv_wr32(dev, 0x700000 + pgt3, ((chan + i) >> 8) | 1);
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nv_wr32(dev, 0x700004 + pgt3, 0);
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}
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/* clear rest of pgt */
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for (; i < dev_priv->ramin_size; i += 4096, pgt3 += 8) {
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nv_wr32(dev, 0x700000 + pgt3, 0);
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nv_wr32(dev, 0x700004 + pgt3, 0);
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}
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/* point bar3 at the channel */
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nv_wr32(dev, 0x001714, 0xc0000000 | (chan >> 12));
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/* Global PRAMIN heap */
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ret = drm_mm_init(&dev_priv->ramin_heap, imem,
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dev_priv->ramin_size - imem);
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if (ret) {
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NV_ERROR(dev, "Failed to init RAMIN heap\n");
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return -ENOMEM;
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}
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return 0;
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}
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void
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nvc0_instmem_takedown(struct drm_device *dev)
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{
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}
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