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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c869f77d6a
Add support for the simplest of MediaTek Wi-Fi devices - MT7601U. It is a single stream bgn chip with no bells or whistles. This driver is partially based on Felix's mt76 but IMHO it doesn't make sense to merge the two right now because MT7601U is a design somewhere between old Ralink devices and new Mediatek chips. There wouldn't be all that much code sharing with the devices mt76 supports. Situation may obviously change when someone decides to extend m76 with support for the more recent USB dongles. The driver supports only station mode. I'm hoping to add AP support when time allows. This driver sat on GitHub for quite a while and got some testing there: http://github.com/kuba-moo/mt7601u Signed-off-by: Jakub Kicinski <kubakici@wp.pl> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
128 lines
3.3 KiB
C
128 lines
3.3 KiB
C
/*
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* Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MT7601U_DMA_H
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#define __MT7601U_DMA_H
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#include <asm/unaligned.h>
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#include <linux/skbuff.h>
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#include "util.h"
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#define MT_DMA_HDR_LEN 4
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#define MT_RX_INFO_LEN 4
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#define MT_FCE_INFO_LEN 4
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#define MT_DMA_HDRS (MT_DMA_HDR_LEN + MT_RX_INFO_LEN)
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/* Common Tx DMA descriptor fields */
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#define MT_TXD_INFO_LEN GENMASK(15, 0)
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#define MT_TXD_INFO_D_PORT GENMASK(29, 27)
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#define MT_TXD_INFO_TYPE GENMASK(31, 30)
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enum mt76_msg_port {
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WLAN_PORT,
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CPU_RX_PORT,
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CPU_TX_PORT,
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HOST_PORT,
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VIRTUAL_CPU_RX_PORT,
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VIRTUAL_CPU_TX_PORT,
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DISCARD,
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};
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enum mt76_info_type {
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DMA_PACKET,
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DMA_COMMAND,
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};
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/* Tx DMA packet specific flags */
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#define MT_TXD_PKT_INFO_NEXT_VLD BIT(16)
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#define MT_TXD_PKT_INFO_TX_BURST BIT(17)
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#define MT_TXD_PKT_INFO_80211 BIT(19)
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#define MT_TXD_PKT_INFO_TSO BIT(20)
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#define MT_TXD_PKT_INFO_CSO BIT(21)
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#define MT_TXD_PKT_INFO_WIV BIT(24)
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#define MT_TXD_PKT_INFO_QSEL GENMASK(26, 25)
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enum mt76_qsel {
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MT_QSEL_MGMT,
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MT_QSEL_HCCA,
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MT_QSEL_EDCA,
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MT_QSEL_EDCA_2,
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};
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/* Tx DMA MCU command specific flags */
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#define MT_TXD_CMD_INFO_SEQ GENMASK(19, 16)
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#define MT_TXD_CMD_INFO_TYPE GENMASK(26, 20)
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static inline int mt7601u_dma_skb_wrap(struct sk_buff *skb,
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enum mt76_msg_port d_port,
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enum mt76_info_type type, u32 flags)
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{
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u32 info;
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/* Buffer layout:
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* | 4B | xfer len | pad | 4B |
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* | TXINFO | pkt/cmd | zero pad to 4B | zero |
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*
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* length field of TXINFO should be set to 'xfer len'.
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*/
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info = flags |
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MT76_SET(MT_TXD_INFO_LEN, round_up(skb->len, 4)) |
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MT76_SET(MT_TXD_INFO_D_PORT, d_port) |
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MT76_SET(MT_TXD_INFO_TYPE, type);
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put_unaligned_le32(info, skb_push(skb, sizeof(info)));
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return skb_put_padto(skb, round_up(skb->len, 4) + 4);
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}
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static inline int
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mt7601u_dma_skb_wrap_pkt(struct sk_buff *skb, enum mt76_qsel qsel, u32 flags)
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{
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flags |= MT76_SET(MT_TXD_PKT_INFO_QSEL, qsel);
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return mt7601u_dma_skb_wrap(skb, WLAN_PORT, DMA_PACKET, flags);
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}
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/* Common Rx DMA descriptor fields */
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#define MT_RXD_INFO_LEN GENMASK(13, 0)
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#define MT_RXD_INFO_PCIE_INTR BIT(24)
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#define MT_RXD_INFO_QSEL GENMASK(26, 25)
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#define MT_RXD_INFO_PORT GENMASK(29, 27)
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#define MT_RXD_INFO_TYPE GENMASK(31, 30)
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/* Rx DMA packet specific flags */
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#define MT_RXD_PKT_INFO_UDP_ERR BIT(16)
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#define MT_RXD_PKT_INFO_TCP_ERR BIT(17)
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#define MT_RXD_PKT_INFO_IP_ERR BIT(18)
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#define MT_RXD_PKT_INFO_PKT_80211 BIT(19)
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#define MT_RXD_PKT_INFO_L3L4_DONE BIT(20)
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#define MT_RXD_PKT_INFO_MAC_LEN GENMASK(23, 21)
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/* Rx DMA MCU command specific flags */
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#define MT_RXD_CMD_INFO_SELF_GEN BIT(15)
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#define MT_RXD_CMD_INFO_CMD_SEQ GENMASK(19, 16)
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#define MT_RXD_CMD_INFO_EVT_TYPE GENMASK(23, 20)
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enum mt76_evt_type {
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CMD_DONE,
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CMD_ERROR,
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CMD_RETRY,
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EVENT_PWR_RSP,
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EVENT_WOW_RSP,
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EVENT_CARRIER_DETECT_RSP,
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EVENT_DFS_DETECT_RSP,
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};
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#endif
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