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f87ccd2edc
this addresses the clock driver aka provider's side of clocks - introduce a 'clocks' subtree with an 'osc' node for the crystal or oscillator SoC input (fixed frequency) - the 'clock@f00' clock-control-module node references the 'osc' for its input, and is another provider for all the clocks which the CCM component manages - prepare for future references to clocks from peripheral nodes by means of the <&clks ID> syntax and symbolic ID names which a header file provides - provide default values with 33MHz oscillator frequency in the common include (the 66MHz IPS bus already was there), and add override values for the ifm AC14xx board which deviates from the reference design (25MHz xtal, 80MHz IPS bus) Cc: Rob Herring <rob.herring@calxeda.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Ian Campbell <ian.campbell@citrix.com> Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Reviewed-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Gerhard Sittig <gsi@denx.de> Signed-off-by: Anatolij Gustschin <agust@denx.de>
400 lines
7.9 KiB
Plaintext
400 lines
7.9 KiB
Plaintext
/*
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* Device Tree Source for the MPC5121e based ac14xx board
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*
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* Copyright 2012 Anatolij Gustschin <agust@denx.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <mpc5121.dtsi>
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/ {
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model = "ac14xx";
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compatible = "ifm,ac14xx", "fsl,mpc5121";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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serial0 = &serial0;
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serial1 = &serial7;
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spi4 = &spi4;
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spi5 = &spi5;
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};
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cpus {
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PowerPC,5121@0 {
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timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
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bus-frequency = <160000000>; /* 160 MHz csb bus */
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clock-frequency = <400000000>; /* 400 MHz ppc core */
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};
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};
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memory {
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reg = <0x00000000 0x10000000>; /* 256MB at 0 */
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};
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nfc@40000000 {
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status = "disabled";
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};
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localbus@80000020 {
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ranges = <0x0 0x0 0xfc000000 0x04000000 /* CS0: NOR flash */
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0x1 0x0 0xe0000000 0x00010000 /* CS1: FRAM */
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0x2 0x0 0xe0100000 0x00080000 /* CS2: asi1 */
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0x3 0x0 0xe0300000 0x00020000 /* CS3: comm */
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0x5 0x0 0xe0400000 0x00010000 /* CS5: safety */
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0x6 0x0 0xe0200000 0x00080000>; /* CS6: asi2 */
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flash@0,0 {
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compatible = "cfi-flash";
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reg = <0 0x00000000 0x04000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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bank-width = <2>;
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device-width = <2>;
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partition@0 {
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label = "dtb-kernel-production";
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reg = <0x00000000 0x00400000>;
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};
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partition@1 {
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label = "filesystem-production";
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reg = <0x00400000 0x03400000>;
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};
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partition@2 {
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label = "recovery";
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reg = <0x03800000 0x00700000>;
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};
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partition@3 {
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label = "uboot-code";
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reg = <0x03f00000 0x00040000>;
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};
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partition@4 {
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label = "uboot-env1";
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reg = <0x03f40000 0x00020000>;
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};
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partition@5 {
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label = "uboot-env2";
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reg = <0x03f60000 0x00020000>;
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};
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};
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fram@1,0 {
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compatible = "ifm,ac14xx-fram", "linux,uio-pdrv-genirq";
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reg = <1 0x00000000 0x00010000>;
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};
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asi@2,0 {
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/* masters mapping: CS, CS offset, size */
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reg = <2 0x00000000 0x00080000
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6 0x00000000 0x00080000>;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ifm,ac14xx-asi-fpga";
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gpios = <
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&gpio_pic 26 0 /* prog */
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&gpio_pic 27 0 /* done */
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&gpio_pic 10 0 /* reset */
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>;
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master@1 {
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interrupts = <20 0x2>;
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interrupt-parent = <&gpio_pic>;
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chipselect = <2 0x00009000 0x00009100>;
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label = "AS-i master 1";
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};
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master@2 {
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interrupts = <21 0x2>;
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interrupt-parent = <&gpio_pic>;
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chipselect = <6 0x00009000 0x00009100>;
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label = "AS-i master 2";
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};
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};
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netx@3,0 {
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compatible = "ifm,netx";
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reg = <0x3 0x00000000 0x00020000>;
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chipselect = <3 0x00101140 0x00203100>;
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interrupts = <17 0x8>;
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gpios = <&gpio_pic 15 0>;
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};
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safety@5,0 {
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compatible = "ifm,safety";
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reg = <0x5 0x00000000 0x00010000>;
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chipselect = <5 0x00009000 0x00009100>;
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interrupts = <22 0x2>;
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interrupt-parent = <&gpio_pic>;
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gpios = <
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&gpio_pic 12 0 /* prog */
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&gpio_pic 11 0 /* done */
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>;
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};
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};
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clocks {
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osc {
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clock-frequency = <25000000>;
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};
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};
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soc@80000000 {
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bus-frequency = <80000000>; /* 80 MHz ips bus */
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clock@f00 {
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compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
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};
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/*
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* GPIO PIC:
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* interrupts cell = <pin nr, sense>
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* sense == 8: Level, low assertion
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* sense == 2: Edge, high-to-low change
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*/
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gpio_pic: gpio@1100 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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sdhc@1500 {
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cd-gpios = <&gpio_pic 23 0>; /* card detect */
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wp-gpios = <&gpio_pic 24 0>; /* write protect */
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wp-inverted; /* WP active high */
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};
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i2c@1700 {
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/* use Fast-mode */
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clock-frequency = <400000>;
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at24@30 {
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compatible = "at24,24c01";
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reg = <0x30>;
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};
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at24@31 {
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compatible = "at24,24c01";
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reg = <0x31>;
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};
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temp@48 {
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compatible = "ad,ad7414";
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reg = <0x48>;
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};
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at24@50 {
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compatible = "at24,24c01";
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reg = <0x50>;
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};
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at24@51 {
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compatible = "at24,24c01";
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reg = <0x51>;
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};
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at24@52 {
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compatible = "at24,24c01";
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reg = <0x52>;
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};
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at24@53 {
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compatible = "at24,24c01";
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reg = <0x53>;
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};
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at24@54 {
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compatible = "at24,24c01";
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reg = <0x54>;
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};
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at24@55 {
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compatible = "at24,24c01";
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reg = <0x55>;
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};
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at24@56 {
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compatible = "at24,24c01";
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reg = <0x56>;
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};
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at24@57 {
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compatible = "at24,24c01";
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reg = <0x57>;
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};
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rtc@68 {
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compatible = "stm,m41t00";
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reg = <0x68>;
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};
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};
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axe_pic: axe-base@2000 {
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compatible = "fsl,mpc5121-axe-base";
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reg = <0x2000 0x100>;
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interrupts = <42 0x8>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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axe-app {
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compatible = "fsl,mpc5121-axe-app";
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interrupt-parent = <&axe_pic>;
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interrupts = <
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/* soft interrupts */
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0 0x0 1 0x0 2 0x0 3 0x0
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4 0x0 5 0x0 6 0x0 7 0x0
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/* fifo interrupts */
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8 0x0 9 0x0 10 0x0 11 0x0
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>;
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};
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display@2100 {
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edid = [00 FF FF FF FF FF FF 00 14 94 00 00 00 00 00 00
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0A 12 01 03 80 1C 23 78 CA 88 FF 94 52 54 8E 27
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1E 4C 50 00 00 00 01 01 01 01 01 01 01 01 01 01
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01 01 01 01 01 01 FB 00 B0 14 00 DC 05 00 08 04
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21 00 1C 23 00 00 00 18 00 00 00 FD 00 38 3C 1F
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3C 01 0A 20 20 20 20 20 20 20 00 00 00 FC 00 45
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54 30 31 38 30 30 33 44 4D 55 0A 0A 00 00 00 10
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00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D5];
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};
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can@2300 {
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status = "disabled";
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};
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can@2380 {
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status = "disabled";
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};
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viu@2400 {
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status = "disabled";
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};
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mdio@2800 {
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phy0: ethernet-phy@1f {
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compatible = "smsc,lan8700";
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reg = <0x1f>;
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};
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};
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enet: ethernet@2800 {
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phy-handle = <&phy0>;
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};
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usb@3000 {
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status = "disabled";
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};
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usb@4000 {
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status = "disabled";
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};
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/* PSC3 serial port A, aka ttyPSC0 */
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serial0: psc@11300 {
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
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fsl,rx-fifo-size = <512>;
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fsl,tx-fifo-size = <512>;
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};
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/* PSC4 in SPI mode */
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spi4: psc@11400 {
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compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
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fsl,rx-fifo-size = <768>;
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fsl,tx-fifo-size = <768>;
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#address-cells = <1>;
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#size-cells = <0>;
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num-cs = <1>;
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cs-gpios = <&gpio_pic 25 0>;
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flash: m25p128@0 {
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compatible = "st,m25p128";
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spi-max-frequency = <20000000>;
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "spi-flash0";
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reg = <0x00000000 0x01000000>;
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};
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};
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};
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/* PSC5 in SPI mode */
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spi5: psc@11500 {
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compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
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fsl,mode = "spi-master";
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fsl,rx-fifo-size = <128>;
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fsl,tx-fifo-size = <128>;
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#address-cells = <1>;
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#size-cells = <0>;
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lcd@0 {
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compatible = "ilitek,ili922x";
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reg = <0>;
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spi-max-frequency = <100000>;
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spi-cpol;
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spi-cpha;
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};
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};
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/* PSC7 serial port C, aka ttyPSC2 */
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serial7: psc@11700 {
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
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fsl,rx-fifo-size = <512>;
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fsl,tx-fifo-size = <512>;
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};
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matrix_keypad@0 {
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compatible = "gpio-matrix-keypad";
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debounce-delay-ms = <5>;
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col-scan-delay-us = <1>;
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gpio-activelow;
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col-gpios-binary;
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col-switch-delay-ms = <200>;
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col-gpios = <&gpio_pic 1 0>; /* pin1 */
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row-gpios = <&gpio_pic 2 0 /* pin2 */
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&gpio_pic 3 0 /* pin3 */
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&gpio_pic 4 0>; /* pin4 */
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linux,keymap = <0x0000006e /* FN LEFT */
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0x01000067 /* UP */
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0x02000066 /* FN RIGHT */
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0x00010069 /* LEFT */
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0x0101006a /* DOWN */
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0x0201006c>; /* RIGHT */
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};
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};
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leds {
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compatible = "gpio-leds";
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backlight {
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label = "backlight";
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gpios = <&gpio_pic 0 0>;
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default-state = "keep";
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};
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green {
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label = "green";
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gpios = <&gpio_pic 18 0>;
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default-state = "keep";
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};
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red {
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label = "red";
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gpios = <&gpio_pic 19 0>;
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default-state = "keep";
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};
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};
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};
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