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270c10e00a
For atomic backoff, we just loop over an exponentially backed off counter. This is extremely ineffective as it doesn't actually yield the cpu strand so that other competing strands can use the cpu core. In cpus previous to SPARC-T4 we have to do this in a slightly hackish way, by doing an operation with no side effects that also happens to mark the strand as unavailable. The mechanism we choose for this is three reads of the %ccr (condition-code) register into %g0 (the zero register). SPARC-T4 has an explicit "pause" instruction, and we'll make use of that in a subsequent commit. Yield strands also in cpu_relax(). We really should have done this a very long time ago. Signed-off-by: David S. Miller <davem@davemloft.net>
40 lines
669 B
C
40 lines
669 B
C
#ifndef _SPARC64_BACKOFF_H
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#define _SPARC64_BACKOFF_H
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#define BACKOFF_LIMIT (4 * 1024)
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#ifdef CONFIG_SMP
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#define BACKOFF_SETUP(reg) \
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mov 1, reg
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#define BACKOFF_LABEL(spin_label, continue_label) \
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spin_label
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#define BACKOFF_SPIN(reg, tmp, label) \
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mov reg, tmp; \
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88: rd %ccr, %g0; \
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rd %ccr, %g0; \
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rd %ccr, %g0; \
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brnz,pt tmp, 88b; \
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sub tmp, 1, tmp; \
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set BACKOFF_LIMIT, tmp; \
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cmp reg, tmp; \
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bg,pn %xcc, label; \
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nop; \
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ba,pt %xcc, label; \
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sllx reg, 1, reg;
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#else
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#define BACKOFF_SETUP(reg)
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#define BACKOFF_LABEL(spin_label, continue_label) \
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continue_label
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#define BACKOFF_SPIN(reg, tmp, label)
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#endif
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#endif /* _SPARC64_BACKOFF_H */
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