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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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f0948f59db
Having fixed factors/dividers in hardware is a common pattern, so add a basic clock type doing this. It basically describes a fixed factor clock using a nominator and a denominator. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Viresh Kumar <viresh.kumar@st.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> [mturquette@linaro.org: constify parent_names in static init macro] [mturquette@linaro.org: copy/paste bug from mux in static init macro] [mturquette@linaro.org: fix error handling in clk_register_fixed_factor] [mturquette@linaro.org: improve division accuracy; thanks to Saravana] Signed-off-by: Mike Turquette <mturquette@linaro.org>
96 lines
2.4 KiB
C
96 lines
2.4 KiB
C
/*
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* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Standard functionality for the common clock API.
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*/
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#include <linux/module.h>
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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/*
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* DOC: basic fixed multiplier and divider clock that cannot gate
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*
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* Traits of this clock:
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* prepare - clk_prepare only ensures that parents are prepared
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* enable - clk_enable only ensures that parents are enabled
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* rate - rate is fixed. clk->rate = parent->rate / div * mult
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* parent - fixed parent. No clk_set_parent support
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*/
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#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
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static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
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return parent_rate * fix->mult / fix->div;
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}
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static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
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if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
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unsigned long best_parent;
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best_parent = (rate / fix->mult) * fix->div;
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*prate = __clk_round_rate(__clk_get_parent(hw->clk),
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best_parent);
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}
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return (*prate / fix->div) * fix->mult;
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}
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static int clk_factor_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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return 0;
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}
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struct clk_ops clk_fixed_factor_ops = {
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.round_rate = clk_factor_round_rate,
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.set_rate = clk_factor_set_rate,
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.recalc_rate = clk_factor_recalc_rate,
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};
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EXPORT_SYMBOL_GPL(clk_fixed_factor_ops);
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struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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unsigned int mult, unsigned int div)
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{
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struct clk_fixed_factor *fix;
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struct clk_init_data init;
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struct clk *clk;
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fix = kmalloc(sizeof(*fix), GFP_KERNEL);
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if (!fix) {
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pr_err("%s: could not allocate fixed factor clk\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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/* struct clk_fixed_factor assignments */
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fix->mult = mult;
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fix->div = div;
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fix->hw.init = &init;
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init.name = name;
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init.ops = &clk_fixed_factor_ops;
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init.flags = flags;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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clk = clk_register(dev, &fix->hw);
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if (IS_ERR(clk))
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kfree(fix);
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return clk;
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}
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