mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
e87eb585d3
- Add NumaChip SPDX header (Krzysztof Wilczynski)
- Replace EXTRA_CFLAGS with ccflags-y (Krzysztof Wilczynski)
- Remove unused includes (Krzysztof Wilczynski)
- Avoid AMD FCH XHCI USB PME# from D0 defect that prevents wakeup on USB
2.0 or 1.1 connect events (Kai-Heng Feng)
- Removed unused sysfs attribute groups (Ben Dooks)
- Remove PTM and ASPM dependencies on PCIEPORTBUS (Bjorn Helgaas)
- Add PCIe Link Control 2 register field definitions to replace magic
numbers in AMDGPU and Radeon CIK/SI (Bjorn Helgaas)
- Fix incorrect Link Control 2 Transmit Margin usage in AMDGPU and Radeon
CIK/SI PCIe Gen3 link training (Bjorn Helgaas)
- Use pcie_capability_read_word() instead of pci_read_config_word() in
AMDGPU and Radeon CIK/SI (Frederick Lawler)
* pci/misc:
drm/radeon: Prefer pcie_capability_read_word()
drm/radeon: Replace numbers with PCI_EXP_LNKCTL2 definitions
drm/radeon: Correct Transmit Margin masks
drm/amdgpu: Prefer pcie_capability_read_word()
drm/amdgpu: Replace numbers with PCI_EXP_LNKCTL2 definitions
drm/amdgpu: Correct Transmit Margin masks
PCI: Add #defines for Enter Compliance, Transmit Margin
PCI: Allow building PCIe things without PCIEPORTBUS
PCI: Remove PCIe Kconfig dependencies on PCI
PCI/ASPM: Remove dependency on PCIEPORTBUS
PCI/PTM: Remove dependency on PCIEPORTBUS
PCI/PTM: Remove spurious "d" from granularity message
PCI: sysfs: Remove unused attribute groups
x86/PCI: Avoid AMD FCH XHCI USB PME# from D0 defect
PCI: Remove unused includes and superfluous struct declaration
x86/PCI: Replace deprecated EXTRA_CFLAGS with ccflags-y
x86/PCI: Correct SPDX comment style
x86/PCI: Add NumaChip SPDX GPL-2.0 to replace COPYING boilerplate
143 lines
3.9 KiB
Plaintext
143 lines
3.9 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
|
|
#
|
|
# PCI Express Port Bus Configuration
|
|
#
|
|
config PCIEPORTBUS
|
|
bool "PCI Express Port Bus support"
|
|
help
|
|
This enables PCI Express Port Bus support. Users can then enable
|
|
support for Native Hot-Plug, Advanced Error Reporting, Power
|
|
Management Events, and Downstream Port Containment.
|
|
|
|
#
|
|
# Include service Kconfig here
|
|
#
|
|
config HOTPLUG_PCI_PCIE
|
|
bool "PCI Express Hotplug driver"
|
|
depends on HOTPLUG_PCI && PCIEPORTBUS
|
|
help
|
|
Say Y here if you have a motherboard that supports PCI Express Native
|
|
Hotplug
|
|
|
|
When in doubt, say N.
|
|
|
|
config PCIEAER
|
|
bool "PCI Express Advanced Error Reporting support"
|
|
depends on PCIEPORTBUS
|
|
select RAS
|
|
default y
|
|
help
|
|
This enables PCI Express Root Port Advanced Error Reporting
|
|
(AER) driver support. Error reporting messages sent to Root
|
|
Port will be handled by PCI Express AER driver.
|
|
|
|
config PCIEAER_INJECT
|
|
tristate "PCI Express error injection support"
|
|
depends on PCIEAER
|
|
help
|
|
This enables PCI Express Root Port Advanced Error Reporting
|
|
(AER) software error injector.
|
|
|
|
Debugging AER code is quite difficult because it is hard
|
|
to trigger various real hardware errors. Software-based
|
|
error injection can fake almost all kinds of errors with the
|
|
help of a user space helper tool aer-inject, which can be
|
|
gotten from:
|
|
http://www.kernel.org/pub/linux/utils/pci/aer-inject/
|
|
|
|
#
|
|
# PCI Express ECRC
|
|
#
|
|
config PCIE_ECRC
|
|
bool "PCI Express ECRC settings control"
|
|
depends on PCIEAER
|
|
help
|
|
Used to override firmware/bios settings for PCI Express ECRC
|
|
(transaction layer end-to-end CRC checking).
|
|
|
|
When in doubt, say N.
|
|
|
|
#
|
|
# PCI Express ASPM
|
|
#
|
|
config PCIEASPM
|
|
bool "PCI Express ASPM control" if EXPERT
|
|
default y
|
|
help
|
|
This enables OS control over PCI Express ASPM (Active State
|
|
Power Management) and Clock Power Management. ASPM supports
|
|
state L0/L0s/L1.
|
|
|
|
ASPM is initially set up by the firmware. With this option enabled,
|
|
Linux can modify this state in order to disable ASPM on known-bad
|
|
hardware or configurations and enable it when known-safe.
|
|
|
|
ASPM can be disabled or enabled at runtime via
|
|
/sys/module/pcie_aspm/parameters/policy
|
|
|
|
When in doubt, say Y.
|
|
|
|
choice
|
|
prompt "Default ASPM policy"
|
|
default PCIEASPM_DEFAULT
|
|
depends on PCIEASPM
|
|
|
|
config PCIEASPM_DEFAULT
|
|
bool "BIOS default"
|
|
depends on PCIEASPM
|
|
help
|
|
Use the BIOS defaults for PCI Express ASPM.
|
|
|
|
config PCIEASPM_POWERSAVE
|
|
bool "Powersave"
|
|
depends on PCIEASPM
|
|
help
|
|
Enable PCI Express ASPM L0s and L1 where possible, even if the
|
|
BIOS did not.
|
|
|
|
config PCIEASPM_POWER_SUPERSAVE
|
|
bool "Power Supersave"
|
|
depends on PCIEASPM
|
|
help
|
|
Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where
|
|
possible. This would result in higher power savings while staying in L1
|
|
where the components support it.
|
|
|
|
config PCIEASPM_PERFORMANCE
|
|
bool "Performance"
|
|
depends on PCIEASPM
|
|
help
|
|
Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.
|
|
endchoice
|
|
|
|
config PCIE_PME
|
|
def_bool y
|
|
depends on PCIEPORTBUS && PM
|
|
|
|
config PCIE_DPC
|
|
bool "PCI Express Downstream Port Containment support"
|
|
depends on PCIEPORTBUS && PCIEAER
|
|
help
|
|
This enables PCI Express Downstream Port Containment (DPC)
|
|
driver support. DPC events from Root and Downstream ports
|
|
will be handled by the DPC driver. If your system doesn't
|
|
have this capability or you do not want to use this feature,
|
|
it is safe to answer N.
|
|
|
|
config PCIE_PTM
|
|
bool "PCI Express Precision Time Measurement support"
|
|
help
|
|
This enables PCI Express Precision Time Measurement (PTM)
|
|
support.
|
|
|
|
This is only useful if you have devices that support PTM, but it
|
|
is safe to enable even if you don't.
|
|
|
|
config PCIE_BW
|
|
bool "PCI Express Bandwidth Change Notification"
|
|
depends on PCIEPORTBUS
|
|
help
|
|
This enables PCI Express Bandwidth Change Notification. If
|
|
you know link width or rate changes occur only to correct
|
|
unreliable links, you may answer Y.
|