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06a9750edc
The PUSH_AND_CLEAR_REGS macro zeroes each register immediately after
pushing it. If an NMI or exception hits after a register is cleared,
but before the UNWIND_HINT_REGS annotation, the ORC unwinder will
wrongly think the previous value of the register was zero. This can
confuse the unwinding process and cause it to exit early.
Because ORC is simpler than DWARF, there are a limited number of unwind
annotation states, so it's not possible to add an individual unwind hint
after each push/clear combination. Instead, the register clearing
instructions need to be consolidated and moved to after the
UNWIND_HINT_REGS annotation.
Fixes: 3f01daecd5 ("x86/entry/64: Introduce the PUSH_AND_CLEAN_REGS macro")
Reviewed-by: Miroslav Benes <mbenes@suse.cz>
Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Dave Jones <dsj@fb.com>
Cc: Jann Horn <jannh@google.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: https://lore.kernel.org/r/68fd3d0bc92ae2d62ff7879d15d3684217d51f08.1587808742.git.jpoimboe@redhat.com
371 lines
10 KiB
C
371 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#include <linux/jump_label.h>
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#include <asm/unwind_hints.h>
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#include <asm/cpufeatures.h>
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#include <asm/page_types.h>
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#include <asm/percpu.h>
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#include <asm/asm-offsets.h>
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#include <asm/processor-flags.h>
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/*
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x86 function call convention, 64-bit:
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-------------------------------------
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arguments | callee-saved | extra caller-saved | return
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[callee-clobbered] | | [callee-clobbered] |
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---------------------------------------------------------------------------
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rdi rsi rdx rcx r8-9 | rbx rbp [*] r12-15 | r10-11 | rax, rdx [**]
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( rsp is obviously invariant across normal function calls. (gcc can 'merge'
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functions when it sees tail-call optimization possibilities) rflags is
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clobbered. Leftover arguments are passed over the stack frame.)
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[*] In the frame-pointers case rbp is fixed to the stack frame.
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[**] for struct return values wider than 64 bits the return convention is a
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bit more complex: up to 128 bits width we return small structures
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straight in rax, rdx. For structures larger than that (3 words or
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larger) the caller puts a pointer to an on-stack return struct
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[allocated in the caller's stack frame] into the first argument - i.e.
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into rdi. All other arguments shift up by one in this case.
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Fortunately this case is rare in the kernel.
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For 32-bit we have the following conventions - kernel is built with
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-mregparm=3 and -freg-struct-return:
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x86 function calling convention, 32-bit:
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----------------------------------------
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arguments | callee-saved | extra caller-saved | return
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[callee-clobbered] | | [callee-clobbered] |
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-------------------------------------------------------------------------
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eax edx ecx | ebx edi esi ebp [*] | <none> | eax, edx [**]
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( here too esp is obviously invariant across normal function calls. eflags
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is clobbered. Leftover arguments are passed over the stack frame. )
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[*] In the frame-pointers case ebp is fixed to the stack frame.
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[**] We build with -freg-struct-return, which on 32-bit means similar
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semantics as on 64-bit: edx can be used for a second return value
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(i.e. covering integer and structure sizes up to 64 bits) - after that
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it gets more complex and more expensive: 3-word or larger struct returns
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get done in the caller's frame and the pointer to the return struct goes
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into regparm0, i.e. eax - the other arguments shift up and the
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function's register parameters degenerate to regparm=2 in essence.
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*/
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#ifdef CONFIG_X86_64
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/*
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* 64-bit system call stack frame layout defines and helpers,
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* for assembly code:
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*/
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/* The layout forms the "struct pt_regs" on the stack: */
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/*
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* C ABI says these regs are callee-preserved. They aren't saved on kernel entry
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* unless syscall needs a complete, fully filled "struct pt_regs".
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*/
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#define R15 0*8
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#define R14 1*8
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#define R13 2*8
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#define R12 3*8
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#define RBP 4*8
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#define RBX 5*8
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/* These regs are callee-clobbered. Always saved on kernel entry. */
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#define R11 6*8
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#define R10 7*8
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#define R9 8*8
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#define R8 9*8
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#define RAX 10*8
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#define RCX 11*8
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#define RDX 12*8
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#define RSI 13*8
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#define RDI 14*8
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/*
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* On syscall entry, this is syscall#. On CPU exception, this is error code.
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* On hw interrupt, it's IRQ number:
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*/
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#define ORIG_RAX 15*8
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/* Return frame for iretq */
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#define RIP 16*8
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#define CS 17*8
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#define EFLAGS 18*8
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#define RSP 19*8
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#define SS 20*8
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#define SIZEOF_PTREGS 21*8
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.macro PUSH_AND_CLEAR_REGS rdx=%rdx rax=%rax save_ret=0
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.if \save_ret
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pushq %rsi /* pt_regs->si */
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movq 8(%rsp), %rsi /* temporarily store the return address in %rsi */
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movq %rdi, 8(%rsp) /* pt_regs->di (overwriting original return address) */
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.else
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pushq %rdi /* pt_regs->di */
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pushq %rsi /* pt_regs->si */
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.endif
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pushq \rdx /* pt_regs->dx */
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pushq %rcx /* pt_regs->cx */
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pushq \rax /* pt_regs->ax */
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pushq %r8 /* pt_regs->r8 */
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pushq %r9 /* pt_regs->r9 */
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pushq %r10 /* pt_regs->r10 */
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pushq %r11 /* pt_regs->r11 */
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pushq %rbx /* pt_regs->rbx */
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pushq %rbp /* pt_regs->rbp */
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pushq %r12 /* pt_regs->r12 */
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pushq %r13 /* pt_regs->r13 */
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pushq %r14 /* pt_regs->r14 */
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pushq %r15 /* pt_regs->r15 */
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UNWIND_HINT_REGS
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.if \save_ret
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pushq %rsi /* return address on top of stack */
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.endif
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/*
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* Sanitize registers of values that a speculation attack might
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* otherwise want to exploit. The lower registers are likely clobbered
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* well before they could be put to use in a speculative execution
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* gadget.
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*/
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xorl %edx, %edx /* nospec dx */
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xorl %ecx, %ecx /* nospec cx */
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xorl %r8d, %r8d /* nospec r8 */
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xorl %r9d, %r9d /* nospec r9 */
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xorl %r10d, %r10d /* nospec r10 */
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xorl %r11d, %r11d /* nospec r11 */
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xorl %ebx, %ebx /* nospec rbx */
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xorl %ebp, %ebp /* nospec rbp */
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xorl %r12d, %r12d /* nospec r12 */
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xorl %r13d, %r13d /* nospec r13 */
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xorl %r14d, %r14d /* nospec r14 */
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xorl %r15d, %r15d /* nospec r15 */
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.endm
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.macro POP_REGS pop_rdi=1 skip_r11rcx=0
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popq %r15
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popq %r14
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popq %r13
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popq %r12
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popq %rbp
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popq %rbx
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.if \skip_r11rcx
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popq %rsi
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.else
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popq %r11
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.endif
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popq %r10
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popq %r9
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popq %r8
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popq %rax
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.if \skip_r11rcx
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popq %rsi
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.else
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popq %rcx
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.endif
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popq %rdx
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popq %rsi
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.if \pop_rdi
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popq %rdi
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.endif
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.endm
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#ifdef CONFIG_PAGE_TABLE_ISOLATION
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/*
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* PAGE_TABLE_ISOLATION PGDs are 8k. Flip bit 12 to switch between the two
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* halves:
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*/
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#define PTI_USER_PGTABLE_BIT PAGE_SHIFT
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#define PTI_USER_PGTABLE_MASK (1 << PTI_USER_PGTABLE_BIT)
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#define PTI_USER_PCID_BIT X86_CR3_PTI_PCID_USER_BIT
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#define PTI_USER_PCID_MASK (1 << PTI_USER_PCID_BIT)
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#define PTI_USER_PGTABLE_AND_PCID_MASK (PTI_USER_PCID_MASK | PTI_USER_PGTABLE_MASK)
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.macro SET_NOFLUSH_BIT reg:req
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bts $X86_CR3_PCID_NOFLUSH_BIT, \reg
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.endm
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.macro ADJUST_KERNEL_CR3 reg:req
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ALTERNATIVE "", "SET_NOFLUSH_BIT \reg", X86_FEATURE_PCID
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/* Clear PCID and "PAGE_TABLE_ISOLATION bit", point CR3 at kernel pagetables: */
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andq $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg
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.endm
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.macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
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ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
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mov %cr3, \scratch_reg
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ADJUST_KERNEL_CR3 \scratch_reg
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mov \scratch_reg, %cr3
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.Lend_\@:
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.endm
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#define THIS_CPU_user_pcid_flush_mask \
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PER_CPU_VAR(cpu_tlbstate) + TLB_STATE_user_pcid_flush_mask
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.macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
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ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
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mov %cr3, \scratch_reg
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ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
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/*
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* Test if the ASID needs a flush.
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*/
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movq \scratch_reg, \scratch_reg2
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andq $(0x7FF), \scratch_reg /* mask ASID */
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bt \scratch_reg, THIS_CPU_user_pcid_flush_mask
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jnc .Lnoflush_\@
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/* Flush needed, clear the bit */
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btr \scratch_reg, THIS_CPU_user_pcid_flush_mask
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movq \scratch_reg2, \scratch_reg
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jmp .Lwrcr3_pcid_\@
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.Lnoflush_\@:
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movq \scratch_reg2, \scratch_reg
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SET_NOFLUSH_BIT \scratch_reg
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.Lwrcr3_pcid_\@:
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/* Flip the ASID to the user version */
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orq $(PTI_USER_PCID_MASK), \scratch_reg
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.Lwrcr3_\@:
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/* Flip the PGD to the user version */
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orq $(PTI_USER_PGTABLE_MASK), \scratch_reg
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mov \scratch_reg, %cr3
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.Lend_\@:
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.endm
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.macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
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pushq %rax
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SWITCH_TO_USER_CR3_NOSTACK scratch_reg=\scratch_reg scratch_reg2=%rax
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popq %rax
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.endm
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.macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
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ALTERNATIVE "jmp .Ldone_\@", "", X86_FEATURE_PTI
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movq %cr3, \scratch_reg
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movq \scratch_reg, \save_reg
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/*
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* Test the user pagetable bit. If set, then the user page tables
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* are active. If clear CR3 already has the kernel page table
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* active.
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*/
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bt $PTI_USER_PGTABLE_BIT, \scratch_reg
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jnc .Ldone_\@
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ADJUST_KERNEL_CR3 \scratch_reg
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movq \scratch_reg, %cr3
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.Ldone_\@:
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.endm
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.macro RESTORE_CR3 scratch_reg:req save_reg:req
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ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
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ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
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/*
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* KERNEL pages can always resume with NOFLUSH as we do
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* explicit flushes.
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*/
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bt $PTI_USER_PGTABLE_BIT, \save_reg
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jnc .Lnoflush_\@
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/*
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* Check if there's a pending flush for the user ASID we're
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* about to set.
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*/
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movq \save_reg, \scratch_reg
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andq $(0x7FF), \scratch_reg
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bt \scratch_reg, THIS_CPU_user_pcid_flush_mask
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jnc .Lnoflush_\@
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btr \scratch_reg, THIS_CPU_user_pcid_flush_mask
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jmp .Lwrcr3_\@
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.Lnoflush_\@:
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SET_NOFLUSH_BIT \save_reg
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.Lwrcr3_\@:
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/*
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* The CR3 write could be avoided when not changing its value,
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* but would require a CR3 read *and* a scratch register.
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*/
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movq \save_reg, %cr3
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.Lend_\@:
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.endm
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#else /* CONFIG_PAGE_TABLE_ISOLATION=n: */
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.macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
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.endm
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.macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
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.endm
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.macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
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.endm
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.macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
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.endm
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.macro RESTORE_CR3 scratch_reg:req save_reg:req
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.endm
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#endif
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/*
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* Mitigate Spectre v1 for conditional swapgs code paths.
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*
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* FENCE_SWAPGS_USER_ENTRY is used in the user entry swapgs code path, to
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* prevent a speculative swapgs when coming from kernel space.
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*
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* FENCE_SWAPGS_KERNEL_ENTRY is used in the kernel entry non-swapgs code path,
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* to prevent the swapgs from getting speculatively skipped when coming from
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* user space.
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*/
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.macro FENCE_SWAPGS_USER_ENTRY
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ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_USER
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.endm
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.macro FENCE_SWAPGS_KERNEL_ENTRY
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ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_KERNEL
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.endm
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.macro STACKLEAK_ERASE_NOCLOBBER
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#ifdef CONFIG_GCC_PLUGIN_STACKLEAK
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PUSH_AND_CLEAR_REGS
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call stackleak_erase
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POP_REGS
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#endif
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.endm
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#endif /* CONFIG_X86_64 */
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.macro STACKLEAK_ERASE
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#ifdef CONFIG_GCC_PLUGIN_STACKLEAK
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call stackleak_erase
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#endif
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.endm
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/*
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* This does 'call enter_from_user_mode' unless we can avoid it based on
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* kernel config or using the static jump infrastructure.
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*/
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.macro CALL_enter_from_user_mode
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#ifdef CONFIG_CONTEXT_TRACKING
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#ifdef CONFIG_JUMP_LABEL
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STATIC_JUMP_IF_FALSE .Lafter_call_\@, context_tracking_key, def=0
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#endif
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call enter_from_user_mode
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.Lafter_call_\@:
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#endif
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.endm
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#ifdef CONFIG_PARAVIRT_XXL
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#define GET_CR2_INTO(reg) GET_CR2_INTO_AX ; _ASM_MOV %_ASM_AX, reg
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#else
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#define GET_CR2_INTO(reg) _ASM_MOV %cr2, reg
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#endif
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