mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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5c6201e60a
I made a mistake as for naming for this block. The MIO block is not implemented for these 3 SoCs in the first place. The current naming will be a trouble if an SoC with both MIO and SD-ctrl blocks appear in the future. This driver has just been merged in the previous merge window. Rename it before the release. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
123 lines
3.6 KiB
C
123 lines
3.6 KiB
C
/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __CLK_UNIPHIER_H__
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#define __CLK_UNIPHIER_H__
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struct clk_hw;
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struct device;
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struct regmap;
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#define UNIPHIER_CLK_MUX_MAX_PARENTS 8
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enum uniphier_clk_type {
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UNIPHIER_CLK_TYPE_FIXED_FACTOR,
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UNIPHIER_CLK_TYPE_FIXED_RATE,
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UNIPHIER_CLK_TYPE_GATE,
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UNIPHIER_CLK_TYPE_MUX,
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};
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struct uniphier_clk_fixed_factor_data {
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const char *parent_name;
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unsigned int mult;
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unsigned int div;
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};
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struct uniphier_clk_fixed_rate_data {
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unsigned long fixed_rate;
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};
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struct uniphier_clk_gate_data {
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const char *parent_name;
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unsigned int reg;
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unsigned int bit;
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};
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struct uniphier_clk_mux_data {
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const char *parent_names[UNIPHIER_CLK_MUX_MAX_PARENTS];
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unsigned int num_parents;
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unsigned int reg;
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unsigned int masks[UNIPHIER_CLK_MUX_MAX_PARENTS];
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unsigned int vals[UNIPHIER_CLK_MUX_MAX_PARENTS];
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};
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struct uniphier_clk_data {
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const char *name;
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enum uniphier_clk_type type;
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int idx;
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union {
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struct uniphier_clk_fixed_factor_data factor;
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struct uniphier_clk_fixed_rate_data rate;
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struct uniphier_clk_gate_data gate;
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struct uniphier_clk_mux_data mux;
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} data;
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};
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#define UNIPHIER_CLK_FACTOR(_name, _idx, _parent, _mult, _div) \
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{ \
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.name = (_name), \
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.type = UNIPHIER_CLK_TYPE_FIXED_FACTOR, \
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.idx = (_idx), \
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.data.factor = { \
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.parent_name = (_parent), \
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.mult = (_mult), \
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.div = (_div), \
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}, \
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}
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#define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \
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{ \
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.name = (_name), \
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.type = UNIPHIER_CLK_TYPE_GATE, \
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.idx = (_idx), \
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.data.gate = { \
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.parent_name = (_parent), \
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.reg = (_reg), \
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.bit = (_bit), \
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}, \
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}
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struct clk_hw *uniphier_clk_register_fixed_factor(struct device *dev,
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const char *name,
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const struct uniphier_clk_fixed_factor_data *data);
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struct clk_hw *uniphier_clk_register_fixed_rate(struct device *dev,
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const char *name,
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const struct uniphier_clk_fixed_rate_data *data);
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struct clk_hw *uniphier_clk_register_gate(struct device *dev,
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struct regmap *regmap,
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const char *name,
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const struct uniphier_clk_gate_data *data);
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struct clk_hw *uniphier_clk_register_mux(struct device *dev,
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struct regmap *regmap,
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const char *name,
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const struct uniphier_clk_mux_data *data);
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extern const struct uniphier_clk_data uniphier_sld3_sys_clk_data[];
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extern const struct uniphier_clk_data uniphier_ld4_sys_clk_data[];
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extern const struct uniphier_clk_data uniphier_pro4_sys_clk_data[];
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extern const struct uniphier_clk_data uniphier_sld8_sys_clk_data[];
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extern const struct uniphier_clk_data uniphier_pro5_sys_clk_data[];
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extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[];
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extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[];
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extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
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extern const struct uniphier_clk_data uniphier_sld3_mio_clk_data[];
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extern const struct uniphier_clk_data uniphier_pro5_sd_clk_data[];
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extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];
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extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[];
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#endif /* __CLK_UNIPHIER_H__ */
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