mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-03 12:36:46 +07:00
9f754b4a68
Add a DMAC platform device and clock definitions for it on r8a73a4. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
320 lines
9.5 KiB
C
320 lines
9.5 KiB
C
/*
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* r8a73a4 processor support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/of_platform.h>
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#include <linux/platform_data/irq-renesas-irqc.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_dma.h>
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#include <linux/sh_timer.h>
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#include <mach/common.h>
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#include <mach/dma-register.h>
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#include <mach/irqs.h>
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#include <mach/r8a73a4.h>
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#include <asm/mach/arch.h>
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static const struct resource pfc_resources[] = {
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DEFINE_RES_MEM(0xe6050000, 0x9000),
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};
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void __init r8a73a4_pinmux_init(void)
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{
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platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources,
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ARRAY_SIZE(pfc_resources));
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}
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#define SCIF_COMMON(scif_type, baseaddr, irq) \
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.type = scif_type, \
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.mapbase = baseaddr, \
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
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.scbrr_algo_id = SCBRR_ALGO_4, \
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.irqs = SCIx_IRQ_MUXED(irq)
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#define SCIFA_DATA(index, baseaddr, irq) \
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[index] = { \
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SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
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}
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#define SCIFB_DATA(index, baseaddr, irq) \
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[index] = { \
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SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
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.scscr = SCSCR_RE | SCSCR_TE, \
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}
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enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 };
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static const struct plat_sci_port scif[] = {
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SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
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SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
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SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
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SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
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SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
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SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
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};
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static inline void r8a73a4_register_scif(int idx)
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{
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platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
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sizeof(struct plat_sci_port));
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}
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static const struct renesas_irqc_config irqc0_data = {
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.irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
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};
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static const struct resource irqc0_resources[] = {
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DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
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DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
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DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
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DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
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DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
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DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
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DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
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DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
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DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
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DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
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DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
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DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
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DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
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DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
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DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
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DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
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DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
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DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
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DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
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DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
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DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
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DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
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DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
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DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
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DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
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DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
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DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
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DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
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DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
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DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
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DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
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DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
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DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
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};
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static const struct renesas_irqc_config irqc1_data = {
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.irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
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};
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static const struct resource irqc1_resources[] = {
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DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
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DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
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DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
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DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
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DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
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DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
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DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
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DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
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DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
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DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
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DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
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DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
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DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
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DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
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DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
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DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
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DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
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DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
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DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
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DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
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DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
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DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
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DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
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DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
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DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
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DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
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DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
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};
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#define r8a73a4_register_irqc(idx) \
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platform_device_register_resndata(&platform_bus, "renesas_irqc", \
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idx, irqc##idx##_resources, \
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ARRAY_SIZE(irqc##idx##_resources), \
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&irqc##idx##_data, \
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sizeof(struct renesas_irqc_config))
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/* Thermal0 -> Thermal2 */
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static const struct resource thermal0_resources[] = {
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DEFINE_RES_MEM(0xe61f0000, 0x14),
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DEFINE_RES_MEM(0xe61f0100, 0x38),
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DEFINE_RES_MEM(0xe61f0200, 0x38),
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DEFINE_RES_MEM(0xe61f0300, 0x38),
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DEFINE_RES_IRQ(gic_spi(69)),
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};
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#define r8a73a4_register_thermal() \
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platform_device_register_simple("rcar_thermal", -1, \
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thermal0_resources, \
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ARRAY_SIZE(thermal0_resources))
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static struct sh_timer_config cmt10_platform_data = {
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.name = "CMT10",
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.timer_bit = 0,
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.clockevent_rating = 80,
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};
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static struct resource cmt10_resources[] = {
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DEFINE_RES_MEM(0xe6130010, 0x0c),
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DEFINE_RES_MEM(0xe6130000, 0x04),
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DEFINE_RES_IRQ(gic_spi(120)), /* CMT1_0 */
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};
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#define r8a7790_register_cmt(idx) \
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platform_device_register_resndata(&platform_bus, "sh_cmt", \
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idx, cmt##idx##_resources, \
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ARRAY_SIZE(cmt##idx##_resources), \
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&cmt##idx##_platform_data, \
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sizeof(struct sh_timer_config))
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void __init r8a73a4_add_dt_devices(void)
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{
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r8a73a4_register_scif(SCIFA0);
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r8a73a4_register_scif(SCIFA1);
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r8a73a4_register_scif(SCIFB0);
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r8a73a4_register_scif(SCIFB1);
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r8a73a4_register_scif(SCIFB2);
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r8a73a4_register_scif(SCIFB3);
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r8a7790_register_cmt(10);
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}
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/* DMA */
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static const struct sh_dmae_slave_config dma_slaves[] = {
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{
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.slave_id = SHDMA_SLAVE_MMCIF0_TX,
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.addr = 0xee200034,
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.chcr = CHCR_TX(XMIT_SZ_32BIT),
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.mid_rid = 0xd1,
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}, {
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.slave_id = SHDMA_SLAVE_MMCIF0_RX,
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.addr = 0xee200034,
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.chcr = CHCR_RX(XMIT_SZ_32BIT),
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.mid_rid = 0xd2,
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}, {
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.slave_id = SHDMA_SLAVE_MMCIF1_TX,
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.addr = 0xee220034,
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.chcr = CHCR_TX(XMIT_SZ_32BIT),
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.mid_rid = 0xe1,
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}, {
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.slave_id = SHDMA_SLAVE_MMCIF1_RX,
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.addr = 0xee220034,
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.chcr = CHCR_RX(XMIT_SZ_32BIT),
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.mid_rid = 0xe2,
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},
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};
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#define DMAE_CHANNEL(a, b) \
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{ \
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.offset = (a) - 0x20, \
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.dmars = (a) - 0x20 + 0x40, \
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.chclr_bit = (b), \
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.chclr_offset = 0x80 - 0x20, \
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}
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static const struct sh_dmae_channel dma_channels[] = {
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DMAE_CHANNEL(0x8000, 0),
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DMAE_CHANNEL(0x8080, 1),
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DMAE_CHANNEL(0x8100, 2),
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DMAE_CHANNEL(0x8180, 3),
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DMAE_CHANNEL(0x8200, 4),
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DMAE_CHANNEL(0x8280, 5),
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DMAE_CHANNEL(0x8300, 6),
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DMAE_CHANNEL(0x8380, 7),
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DMAE_CHANNEL(0x8400, 8),
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DMAE_CHANNEL(0x8480, 9),
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DMAE_CHANNEL(0x8500, 10),
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DMAE_CHANNEL(0x8580, 11),
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DMAE_CHANNEL(0x8600, 12),
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DMAE_CHANNEL(0x8680, 13),
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DMAE_CHANNEL(0x8700, 14),
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DMAE_CHANNEL(0x8780, 15),
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DMAE_CHANNEL(0x8800, 16),
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DMAE_CHANNEL(0x8880, 17),
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DMAE_CHANNEL(0x8900, 18),
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DMAE_CHANNEL(0x8980, 19),
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};
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static const struct sh_dmae_pdata dma_pdata = {
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.slave = dma_slaves,
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.slave_num = ARRAY_SIZE(dma_slaves),
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.channel = dma_channels,
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.channel_num = ARRAY_SIZE(dma_channels),
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.ts_low_shift = TS_LOW_SHIFT,
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.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
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.ts_high_shift = TS_HI_SHIFT,
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.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
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.ts_shift = dma_ts_shift,
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.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
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.dmaor_init = DMAOR_DME,
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.chclr_present = 1,
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.chclr_bitwise = 1,
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};
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static struct resource dma_resources[] = {
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DEFINE_RES_MEM(0xe6700020, 0x89e0),
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DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"),
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{
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/* IRQ for channels 0-19 */
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.start = gic_spi(200),
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.end = gic_spi(219),
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.flags = IORESOURCE_IRQ,
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},
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};
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#define r8a73a4_register_dmac() \
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platform_device_register_resndata(&platform_bus, "sh-dma-engine", 0, \
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dma_resources, ARRAY_SIZE(dma_resources), \
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&dma_pdata, sizeof(dma_pdata))
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void __init r8a73a4_add_standard_devices(void)
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{
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r8a73a4_add_dt_devices();
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r8a73a4_register_irqc(0);
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r8a73a4_register_irqc(1);
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r8a73a4_register_thermal();
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r8a73a4_register_dmac();
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}
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void __init r8a73a4_init_early(void)
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{
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#ifndef CONFIG_ARM_ARCH_TIMER
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shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */
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#endif
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}
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#ifdef CONFIG_USE_OF
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static const char *r8a73a4_boards_compat_dt[] __initdata = {
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"renesas,r8a73a4",
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NULL,
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};
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DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
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.init_early = r8a73a4_init_early,
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.dt_compat = r8a73a4_boards_compat_dt,
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MACHINE_END
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#endif /* CONFIG_USE_OF */
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