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84f404f695
TARGET_CPUS is the default irq routing poicy. It specifies which cpus the kernel should aim an irq at. In physflat delivery mode we can route an irq to a single cpu. But that doesn't mean our default policy should only be a single cpu is allowed. By allowing the irq routing code to select from multiple cpus this enables systems with more irqs then we can service on a single processor to actually work. I just audited and tested the code and irqbalance doesn't care, and the io_apic.c doesn't care if we have extra cpus in the mask. Everything will use or assume we are using the lowest numbered cpu in the mask if we can't use them all. So this should result in no behavior changes except on systems that need it. Thanks for YH Lu for spotting this problem in his testing. Cc: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Andi Kleen <ak@suse.de>
214 lines
5.1 KiB
C
214 lines
5.1 KiB
C
/*
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* Copyright 2004 James Cleverdon, IBM.
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* Subject to the GNU Public License, v.2
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*
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* Flat APIC subarch code.
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*
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* Hacked for x86-64 by James Cleverdon from i386 architecture code by
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* Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
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* James Cleverdon.
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*/
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#include <linux/threads.h>
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#include <linux/cpumask.h>
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/ctype.h>
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#include <linux/init.h>
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#include <asm/smp.h>
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#include <asm/ipi.h>
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static cpumask_t flat_target_cpus(void)
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{
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return cpu_online_map;
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}
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static cpumask_t flat_vector_allocation_domain(int cpu)
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{
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/* Careful. Some cpus do not strictly honor the set of cpus
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* specified in the interrupt destination when using lowest
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* priority interrupt delivery mode.
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*
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* In particular there was a hyperthreading cpu observed to
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* deliver interrupts to the wrong hyperthread when only one
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* hyperthread was specified in the interrupt desitination.
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*/
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cpumask_t domain = { { [0] = APIC_ALL_CPUS, } };
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return domain;
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}
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/*
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* Set up the logical destination ID.
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*
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* Intel recommends to set DFR, LDR and TPR before enabling
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* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
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* document number 292116). So here it goes...
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*/
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static void flat_init_apic_ldr(void)
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{
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unsigned long val;
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unsigned long num, id;
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num = smp_processor_id();
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id = 1UL << num;
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x86_cpu_to_log_apicid[num] = id;
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apic_write(APIC_DFR, APIC_DFR_FLAT);
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val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
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val |= SET_APIC_LOGICAL_ID(id);
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apic_write(APIC_LDR, val);
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}
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static void flat_send_IPI_mask(cpumask_t cpumask, int vector)
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{
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unsigned long mask = cpus_addr(cpumask)[0];
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unsigned long cfg;
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unsigned long flags;
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local_irq_save(flags);
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/*
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* Wait for idle.
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*/
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apic_wait_icr_idle();
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/*
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* prepare target chip field
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*/
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cfg = __prepare_ICR2(mask);
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apic_write(APIC_ICR2, cfg);
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/*
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* program the ICR
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*/
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cfg = __prepare_ICR(0, vector, APIC_DEST_LOGICAL);
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/*
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* Send the IPI. The write to APIC_ICR fires this off.
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*/
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apic_write(APIC_ICR, cfg);
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local_irq_restore(flags);
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}
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static void flat_send_IPI_allbutself(int vector)
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{
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#ifdef CONFIG_HOTPLUG_CPU
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int hotplug = 1;
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#else
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int hotplug = 0;
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#endif
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if (hotplug || vector == NMI_VECTOR) {
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cpumask_t allbutme = cpu_online_map;
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cpu_clear(smp_processor_id(), allbutme);
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if (!cpus_empty(allbutme))
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flat_send_IPI_mask(allbutme, vector);
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} else if (num_online_cpus() > 1) {
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__send_IPI_shortcut(APIC_DEST_ALLBUT, vector,APIC_DEST_LOGICAL);
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}
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}
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static void flat_send_IPI_all(int vector)
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{
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if (vector == NMI_VECTOR)
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flat_send_IPI_mask(cpu_online_map, vector);
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else
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__send_IPI_shortcut(APIC_DEST_ALLINC, vector, APIC_DEST_LOGICAL);
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}
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static int flat_apic_id_registered(void)
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{
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return physid_isset(GET_APIC_ID(apic_read(APIC_ID)), phys_cpu_present_map);
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}
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static unsigned int flat_cpu_mask_to_apicid(cpumask_t cpumask)
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{
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return cpus_addr(cpumask)[0] & APIC_ALL_CPUS;
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}
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static unsigned int phys_pkg_id(int index_msb)
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{
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return hard_smp_processor_id() >> index_msb;
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}
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struct genapic apic_flat = {
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.name = "flat",
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.int_delivery_mode = dest_LowestPrio,
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.int_dest_mode = (APIC_DEST_LOGICAL != 0),
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.target_cpus = flat_target_cpus,
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.vector_allocation_domain = flat_vector_allocation_domain,
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.apic_id_registered = flat_apic_id_registered,
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.init_apic_ldr = flat_init_apic_ldr,
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.send_IPI_all = flat_send_IPI_all,
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.send_IPI_allbutself = flat_send_IPI_allbutself,
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.send_IPI_mask = flat_send_IPI_mask,
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.cpu_mask_to_apicid = flat_cpu_mask_to_apicid,
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.phys_pkg_id = phys_pkg_id,
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};
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/*
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* Physflat mode is used when there are more than 8 CPUs on a AMD system.
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* We cannot use logical delivery in this case because the mask
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* overflows, so use physical mode.
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*/
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static cpumask_t physflat_target_cpus(void)
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{
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return cpu_online_map;
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}
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static cpumask_t physflat_vector_allocation_domain(int cpu)
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{
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cpumask_t domain = CPU_MASK_NONE;
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cpu_set(cpu, domain);
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return domain;
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}
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static void physflat_send_IPI_mask(cpumask_t cpumask, int vector)
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{
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send_IPI_mask_sequence(cpumask, vector);
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}
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static void physflat_send_IPI_allbutself(int vector)
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{
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cpumask_t allbutme = cpu_online_map;
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cpu_clear(smp_processor_id(), allbutme);
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physflat_send_IPI_mask(allbutme, vector);
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}
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static void physflat_send_IPI_all(int vector)
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{
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physflat_send_IPI_mask(cpu_online_map, vector);
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}
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static unsigned int physflat_cpu_mask_to_apicid(cpumask_t cpumask)
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{
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int cpu;
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/*
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* We're using fixed IRQ delivery, can only return one phys APIC ID.
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* May as well be the first.
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*/
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cpu = first_cpu(cpumask);
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if ((unsigned)cpu < NR_CPUS)
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return x86_cpu_to_apicid[cpu];
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else
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return BAD_APICID;
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}
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struct genapic apic_physflat = {
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.name = "physical flat",
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.int_delivery_mode = dest_Fixed,
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.int_dest_mode = (APIC_DEST_PHYSICAL != 0),
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.target_cpus = physflat_target_cpus,
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.vector_allocation_domain = physflat_vector_allocation_domain,
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.apic_id_registered = flat_apic_id_registered,
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.init_apic_ldr = flat_init_apic_ldr,/*not needed, but shouldn't hurt*/
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.send_IPI_all = physflat_send_IPI_all,
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.send_IPI_allbutself = physflat_send_IPI_allbutself,
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.send_IPI_mask = physflat_send_IPI_mask,
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.cpu_mask_to_apicid = physflat_cpu_mask_to_apicid,
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.phys_pkg_id = phys_pkg_id,
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};
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