mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 21:16:02 +07:00
9896c7b57e
We get support for three new 32-bit SoC platforms this time. The amount of changes in arch/arm for any of them is miniscule, as all the interesting code is in device driver subsystems (irqchip, clk, pinctrl, ...) these days. I'm listing them here, as the addition of the Kconfig statement is the main relevant milestone for a new platform. In each case, some drivers are are shared with existing platforms, while other drivers are added for v4.7 as well, or come in a later release. - The Aspeed platform is probably the most interesting one, this is what most whitebox servers use as their baseboard management controller. We get support for the very common ast2400 and ast2500 SoCs. The OpenBMC project focuses on this chip, and the LWN article about their ELC 2016 presentation at https://lwn.net/Articles/683320/ triggered the submission, but the code comes from IBM's OpenPOWER team rather than the team at Facebook. There are still a lot more drivers that need to get added over time, and I hope both teams can work together on that. - OXNAS is an old platform for Network Attached Storage devices from Oxford Semiconductor. There are models with ARM10 (!) and ARM11MPCore cores, but for now, we only support the original ARM9 based versions. The product lineup was subsequently part of PLX, Avago and now the new Broadcom Ltd. https://wiki.openwrt.org/doc/hardware/soc/soc.oxnas has some more information. - V2M-MPS2 is a prototyping platform from ARM for their Cortex-M cores and is related to the existing Realview / Versatile Express lineup, but without MMU. We now support various NOMMU platforms, so adding a new one is fairly straightforward. http://infocenter.arm.com/help/topic/com.arm.doc.100112_0100_03_en/ has detailed information about the platform. Other noteworthy updates: - Work on LPC32xx has resumed, and Vladimir Zapolskiy and Sylvain Lemieux are now maintaining the platform. This is an older ARM9 based platform from NXP (not Freescale), but it remains in use in embedded markets. - Kevin Hilman is now co-maintaining the Amlogic Meson platform for both 32-bit and 64-bit ARM, and started contributing some patches. - As is often the case, work on the OMAP platforms makes up the bulk of the actual SoC code changes in arch/arm, but there isn't a lot of that either. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIVAwUAVzuXX2CrR//JCVInAQLTghAA0f+2V2wC6HVBfDhT1YmhbAkPF1KzgLbB h30fN6BtIe9mE3kR69uWgwPSzn4hTKEQXoC9m6S+XClTn6MKPrbCEYDZl4ZwIER8 XDamxJV+6oTG+GKtKpHFkC4WPJkLthEuD34gr2xU8DFrU+y2Y5QNXi5wvSsBp8WS 6C/70HQEy35uSyOjbjVlPi0/UKoelVw9dCO7HZBOb9lTd88hC4Gx90KFwpq6Ievf L20VNgOESC2y6kRbuLNbhQVsbT2Ijyz9NccVM5owFEbHkXDxJ0vQVzrNM999DVjb CC2v0NZMLPNJQn2RvC172QBOsOERxIRkZdJHcifydl7i2QNpr8+/YSnS7OSx3dA/ 3ZmTLejaiGUXdTGEI9dHy77s+adwTzGsH+INKotQG8qwUXzCLuUWN3GGK+Qof5Rk jbsGAoZ7GQz1/7NdEOcGW6pxD4mllk3McKMzNlMmddRDUPhSUg3WXu0c1AWGzfA1 ulk6fQDaTUjvs7nokuozhguKz8OKrT6S7x/iES5tPbXLhuDqfnUdYiQ+7m2beRb5 L9S9KK95HXnKJAI9WLOELj1vCrfbCGjlwz8YVSrwPtwwzP/wbB1Ni6tmwLrxHbLk SGyJEMnPs3mARIPDwDysyOs+3OUSx04uYW6YTSh8XyKNIxTCflRxr/iM5YyYEMvt lXMrp1sh4hc= =5oFu -----END PGP SIGNATURE----- Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Arnd Bergmann: "We get support for three new 32-bit SoC platforms this time. The amount of changes in arch/arm for any of them is miniscule, as all the interesting code is in device driver subsystems (irqchip, clk, pinctrl, ...) these days. I'm listing them here, as the addition of the Kconfig statement is the main relevant milestone for a new platform. In each case, some drivers are are shared with existing platforms, while other drivers are added for v4.7 as well, or come in a later release. - The Aspeed platform is probably the most interesting one, this is what most whitebox servers use as their baseboard management controller. We get support for the very common ast2400 and ast2500 SoCs. The OpenBMC project focuses on this chip, and the LWN article about their ELC 2016 presentation at https://lwn.net/Articles/683320/ triggered the submission, but the code comes from IBM's OpenPOWER team rather than the team at Facebook. There are still a lot more drivers that need to get added over time, and I hope both teams can work together on that. - OXNAS is an old platform for Network Attached Storage devices from Oxford Semiconductor. There are models with ARM10 (!) and ARM11MPCore cores, but for now, we only support the original ARM9 based versions. The product lineup was subsequently part of PLX, Avago and now the new Broadcom Ltd. https://wiki.openwrt.org/doc/hardware/soc/soc.oxnas has some more information. - V2M-MPS2 is a prototyping platform from ARM for their Cortex-M cores and is related to the existing Realview / Versatile Express lineup, but without MMU. We now support various NOMMU platforms, so adding a new one is fairly straightforward. http://infocenter.arm.com/help/topic/com.arm.doc.100112_0100_03_en/ has detailed information about the platform. Other noteworthy updates: - Work on LPC32xx has resumed, and Vladimir Zapolskiy and Sylvain Lemieux are now maintaining the platform. This is an older ARM9 based platform from NXP (not Freescale), but it remains in use in embedded markets. - Kevin Hilman is now co-maintaining the Amlogic Meson platform for both 32-bit and 64-bit ARM, and started contributing some patches. - As is often the case, work on the OMAP platforms makes up the bulk of the actual SoC code changes in arch/arm, but there isn't a lot of that either" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (42 commits) MAINTAINERS: ARM/Amlogic: add co-maintainer, misc. updates MAINTAINERS: add ARM/NXP LPC32XX SoC specific drivers to the section MAINTAINERS: add new maintainers of NXP LPC32xx SoC MAINTAINERS: move ARM/NXP LPC32xx record to ARM section arm: Add Aspeed machine ARM: lpc32xx: remove duplicate const on lpc32xx_auxdata_lookup ARM: lpc32xx: remove leftovers of legacy clock source and provider drivers ARM: lpc32xx: remove reboot header file ARM: dove: Remove CLK_IS_ROOT ARM: orion5x: Remove CLK_IS_ROOT ARM: mv78xx0: Remove CLK_IS_ROOT ARM: davinci: da850: use clk->set_parent for async3 ARM: davinci: Move clock init after ioremap. MAINTAINERS: Update ARM Versatile Express platform entry ARM: vexpress/mps2: introduce MPS2 platform MAINTAINERS: add maintainer entry for ARM/OXNAS platform ARM: Add new mach-oxnas irqchip: versatile-fpga: add new compatible for OX810SE SoC ARM: uniphier: correct the call order of of_node_put() MAINTAINERS: fix stale TI DaVinci entries ...
557 lines
14 KiB
C
557 lines
14 KiB
C
/*
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* OMAP WakeupGen Source file
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*
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* OMAP WakeupGen is the interrupt controller extension used along
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* with ARM GIC to wake the CPU out from low power states on
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* external interrupts. It is responsible for generating wakeup
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* event from the incoming interrupts and enable bits. It is
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* implemented in MPU always ON power domain. During normal operation,
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* WakeupGen delivers external interrupts directly to the GIC.
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/cpu.h>
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#include <linux/notifier.h>
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#include <linux/cpu_pm.h>
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#include "omap-wakeupgen.h"
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#include "omap-secure.h"
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#include "soc.h"
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#include "omap4-sar-layout.h"
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#include "common.h"
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#include "pm.h"
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#define AM43XX_NR_REG_BANKS 7
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#define AM43XX_IRQS 224
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#define MAX_NR_REG_BANKS AM43XX_NR_REG_BANKS
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#define MAX_IRQS AM43XX_IRQS
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#define DEFAULT_NR_REG_BANKS 5
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#define DEFAULT_IRQS 160
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#define WKG_MASK_ALL 0x00000000
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#define WKG_UNMASK_ALL 0xffffffff
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#define CPU_ENA_OFFSET 0x400
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#define CPU0_ID 0x0
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#define CPU1_ID 0x1
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#define OMAP4_NR_BANKS 4
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#define OMAP4_NR_IRQS 128
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static void __iomem *wakeupgen_base;
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static void __iomem *sar_base;
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static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
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static unsigned int irq_target_cpu[MAX_IRQS];
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static unsigned int irq_banks = DEFAULT_NR_REG_BANKS;
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static unsigned int max_irqs = DEFAULT_IRQS;
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static unsigned int omap_secure_apis;
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/*
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* Static helper functions.
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*/
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static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
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{
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return readl_relaxed(wakeupgen_base + OMAP_WKG_ENB_A_0 +
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(cpu * CPU_ENA_OFFSET) + (idx * 4));
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}
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static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
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{
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writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
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(cpu * CPU_ENA_OFFSET) + (idx * 4));
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}
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static inline void sar_writel(u32 val, u32 offset, u8 idx)
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{
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writel_relaxed(val, sar_base + offset + (idx * 4));
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}
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static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
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{
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/*
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* Each WakeupGen register controls 32 interrupt.
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* i.e. 1 bit per SPI IRQ
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*/
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*reg_index = irq >> 5;
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*bit_posn = irq %= 32;
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return 0;
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}
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static void _wakeupgen_clear(unsigned int irq, unsigned int cpu)
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{
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u32 val, bit_number;
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u8 i;
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if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
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return;
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val = wakeupgen_readl(i, cpu);
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val &= ~BIT(bit_number);
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wakeupgen_writel(val, i, cpu);
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}
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static void _wakeupgen_set(unsigned int irq, unsigned int cpu)
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{
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u32 val, bit_number;
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u8 i;
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if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
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return;
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val = wakeupgen_readl(i, cpu);
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val |= BIT(bit_number);
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wakeupgen_writel(val, i, cpu);
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}
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/*
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* Architecture specific Mask extension
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*/
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static void wakeupgen_mask(struct irq_data *d)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&wakeupgen_lock, flags);
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_wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]);
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raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
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irq_chip_mask_parent(d);
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}
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/*
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* Architecture specific Unmask extension
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*/
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static void wakeupgen_unmask(struct irq_data *d)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&wakeupgen_lock, flags);
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_wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]);
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raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
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irq_chip_unmask_parent(d);
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
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static void _wakeupgen_save_masks(unsigned int cpu)
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{
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u8 i;
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for (i = 0; i < irq_banks; i++)
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per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
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}
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static void _wakeupgen_restore_masks(unsigned int cpu)
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{
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u8 i;
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for (i = 0; i < irq_banks; i++)
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wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
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}
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static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
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{
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u8 i;
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for (i = 0; i < irq_banks; i++)
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wakeupgen_writel(reg, i, cpu);
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}
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/*
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* Mask or unmask all interrupts on given CPU.
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* 0 = Mask all interrupts on the 'cpu'
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* 1 = Unmask all interrupts on the 'cpu'
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* Ensure that the initial mask is maintained. This is faster than
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* iterating through GIC registers to arrive at the correct masks.
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*/
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static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&wakeupgen_lock, flags);
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if (set) {
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_wakeupgen_save_masks(cpu);
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_wakeupgen_set_all(cpu, WKG_MASK_ALL);
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} else {
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_wakeupgen_set_all(cpu, WKG_UNMASK_ALL);
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_wakeupgen_restore_masks(cpu);
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}
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raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
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}
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#endif
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#ifdef CONFIG_CPU_PM
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static inline void omap4_irq_save_context(void)
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{
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u32 i, val;
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if (omap_rev() == OMAP4430_REV_ES1_0)
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return;
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for (i = 0; i < irq_banks; i++) {
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/* Save the CPUx interrupt mask for IRQ 0 to 127 */
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val = wakeupgen_readl(i, 0);
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sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
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val = wakeupgen_readl(i, 1);
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sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);
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/*
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* Disable the secure interrupts for CPUx. The restore
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* code blindly restores secure and non-secure interrupt
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* masks from SAR RAM. Secure interrupts are not suppose
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* to be enabled from HLOS. So overwrite the SAR location
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* so that the secure interrupt remains disabled.
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*/
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sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
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sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
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}
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/* Save AuxBoot* registers */
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val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
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writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET);
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val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
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writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET);
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/* Save SyncReq generation logic */
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val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
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writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
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val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
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writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET);
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/* Set the Backup Bit Mask status */
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val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET);
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val |= SAR_BACKUP_STATUS_WAKEUPGEN;
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writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
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}
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static inline void omap5_irq_save_context(void)
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{
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u32 i, val;
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for (i = 0; i < irq_banks; i++) {
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/* Save the CPUx interrupt mask for IRQ 0 to 159 */
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val = wakeupgen_readl(i, 0);
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sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
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val = wakeupgen_readl(i, 1);
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sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
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sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
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sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
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}
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/* Save AuxBoot* registers */
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val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
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writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
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val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
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writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
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/* Set the Backup Bit Mask status */
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val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
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val |= SAR_BACKUP_STATUS_WAKEUPGEN;
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writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
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}
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/*
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* Save WakeupGen interrupt context in SAR BANK3. Restore is done by
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* ROM code. WakeupGen IP is integrated along with GIC to manage the
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* interrupt wakeups from CPU low power states. It manages
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* masking/unmasking of Shared peripheral interrupts(SPI). So the
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* interrupt enable/disable control should be in sync and consistent
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* at WakeupGen and GIC so that interrupts are not lost.
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*/
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static void irq_save_context(void)
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{
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/* DRA7 has no SAR to save */
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if (soc_is_dra7xx())
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return;
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if (!sar_base)
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sar_base = omap4_get_sar_ram_base();
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if (soc_is_omap54xx())
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omap5_irq_save_context();
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else
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omap4_irq_save_context();
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}
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/*
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* Clear WakeupGen SAR backup status.
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*/
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static void irq_sar_clear(void)
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{
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u32 val;
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u32 offset = SAR_BACKUP_STATUS_OFFSET;
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/* DRA7 has no SAR to save */
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if (soc_is_dra7xx())
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return;
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if (soc_is_omap54xx())
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offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
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val = readl_relaxed(sar_base + offset);
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val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
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writel_relaxed(val, sar_base + offset);
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}
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/*
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* Save GIC and Wakeupgen interrupt context using secure API
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* for HS/EMU devices.
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*/
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static void irq_save_secure_context(void)
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{
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u32 ret;
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ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX,
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FLAG_START_CRITICAL,
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0, 0, 0, 0, 0);
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if (ret != API_HAL_RET_VALUE_OK)
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pr_err("GIC and Wakeupgen context save failed\n");
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}
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#endif
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#ifdef CONFIG_HOTPLUG_CPU
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static int irq_cpu_hotplug_notify(struct notifier_block *self,
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unsigned long action, void *hcpu)
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{
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unsigned int cpu = (unsigned int)hcpu;
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/*
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* Corresponding FROZEN transitions do not have to be handled,
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* they are handled by at a higher level
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* (drivers/cpuidle/coupled.c).
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*/
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switch (action) {
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case CPU_ONLINE:
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wakeupgen_irqmask_all(cpu, 0);
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break;
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case CPU_DEAD:
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wakeupgen_irqmask_all(cpu, 1);
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block irq_hotplug_notifier = {
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.notifier_call = irq_cpu_hotplug_notify,
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};
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static void __init irq_hotplug_init(void)
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{
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register_hotcpu_notifier(&irq_hotplug_notifier);
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}
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#else
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static void __init irq_hotplug_init(void)
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{}
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#endif
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#ifdef CONFIG_CPU_PM
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static int irq_notifier(struct notifier_block *self, unsigned long cmd, void *v)
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{
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switch (cmd) {
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case CPU_CLUSTER_PM_ENTER:
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if (omap_type() == OMAP2_DEVICE_TYPE_GP)
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irq_save_context();
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else
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irq_save_secure_context();
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break;
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case CPU_CLUSTER_PM_EXIT:
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if (omap_type() == OMAP2_DEVICE_TYPE_GP)
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irq_sar_clear();
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block irq_notifier_block = {
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.notifier_call = irq_notifier,
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};
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static void __init irq_pm_init(void)
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{
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/* FIXME: Remove this when MPU OSWR support is added */
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if (!IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
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cpu_pm_register_notifier(&irq_notifier_block);
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}
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#else
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static void __init irq_pm_init(void)
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{}
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#endif
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void __iomem *omap_get_wakeupgen_base(void)
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{
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return wakeupgen_base;
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}
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int omap_secure_apis_support(void)
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{
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return omap_secure_apis;
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}
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static struct irq_chip wakeupgen_chip = {
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.name = "WUGEN",
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.irq_eoi = irq_chip_eoi_parent,
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.irq_mask = wakeupgen_mask,
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.irq_unmask = wakeupgen_unmask,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_type = irq_chip_set_type_parent,
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.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
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#ifdef CONFIG_SMP
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.irq_set_affinity = irq_chip_set_affinity_parent,
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#endif
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};
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static int wakeupgen_domain_translate(struct irq_domain *d,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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if (is_of_node(fwspec->fwnode)) {
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if (fwspec->param_count != 3)
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return -EINVAL;
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/* No PPI should point to this domain */
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if (fwspec->param[0] != 0)
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return -EINVAL;
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*hwirq = fwspec->param[1];
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*type = fwspec->param[2];
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return 0;
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}
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return -EINVAL;
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}
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static int wakeupgen_domain_alloc(struct irq_domain *domain,
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unsigned int virq,
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unsigned int nr_irqs, void *data)
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{
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struct irq_fwspec *fwspec = data;
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struct irq_fwspec parent_fwspec;
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irq_hw_number_t hwirq;
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int i;
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if (fwspec->param_count != 3)
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return -EINVAL; /* Not GIC compliant */
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if (fwspec->param[0] != 0)
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return -EINVAL; /* No PPI should point to this domain */
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hwirq = fwspec->param[1];
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if (hwirq >= MAX_IRQS)
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return -EINVAL; /* Can't deal with this */
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for (i = 0; i < nr_irqs; i++)
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irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
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&wakeupgen_chip, NULL);
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parent_fwspec = *fwspec;
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parent_fwspec.fwnode = domain->parent->fwnode;
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return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
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&parent_fwspec);
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}
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static const struct irq_domain_ops wakeupgen_domain_ops = {
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.translate = wakeupgen_domain_translate,
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.alloc = wakeupgen_domain_alloc,
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.free = irq_domain_free_irqs_common,
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};
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/*
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* Initialise the wakeupgen module.
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*/
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static int __init wakeupgen_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *parent_domain, *domain;
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int i;
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unsigned int boot_cpu = smp_processor_id();
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u32 val;
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if (!parent) {
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pr_err("%s: no parent, giving up\n", node->full_name);
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return -ENODEV;
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}
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parent_domain = irq_find_host(parent);
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if (!parent_domain) {
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pr_err("%s: unable to obtain parent domain\n", node->full_name);
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return -ENXIO;
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}
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/* Not supported on OMAP4 ES1.0 silicon */
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if (omap_rev() == OMAP4430_REV_ES1_0) {
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WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
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return -EPERM;
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}
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/* Static mapping, never released */
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wakeupgen_base = of_iomap(node, 0);
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if (WARN_ON(!wakeupgen_base))
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return -ENOMEM;
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if (cpu_is_omap44xx()) {
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irq_banks = OMAP4_NR_BANKS;
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max_irqs = OMAP4_NR_IRQS;
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omap_secure_apis = 1;
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} else if (soc_is_am43xx()) {
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irq_banks = AM43XX_NR_REG_BANKS;
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max_irqs = AM43XX_IRQS;
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}
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domain = irq_domain_add_hierarchy(parent_domain, 0, max_irqs,
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node, &wakeupgen_domain_ops,
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NULL);
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if (!domain) {
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iounmap(wakeupgen_base);
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return -ENOMEM;
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}
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/* Clear all IRQ bitmasks at wakeupGen level */
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for (i = 0; i < irq_banks; i++) {
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wakeupgen_writel(0, i, CPU0_ID);
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if (!soc_is_am43xx())
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wakeupgen_writel(0, i, CPU1_ID);
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}
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/*
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* FIXME: Add support to set_smp_affinity() once the core
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* GIC code has necessary hooks in place.
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*/
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/* Associate all the IRQs to boot CPU like GIC init does. */
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for (i = 0; i < max_irqs; i++)
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irq_target_cpu[i] = boot_cpu;
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/*
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* Enables OMAP5 ES2 PM Mode using ES2_PM_MODE in AMBA_IF_MODE
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* 0x0: ES1 behavior, CPU cores would enter and exit OFF mode together.
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* 0x1: ES2 behavior, CPU cores are allowed to enter/exit OFF mode
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* independently.
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* This needs to be set one time thanks to always ON domain.
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*
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* We do not support ES1 behavior anymore. OMAP5 is assumed to be
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* ES2.0, and the same is applicable for DRA7.
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*/
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if (soc_is_omap54xx() || soc_is_dra7xx()) {
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val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE);
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val |= BIT(5);
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omap_smc1(OMAP5_MON_AMBA_IF_INDEX, val);
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}
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irq_hotplug_init();
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irq_pm_init();
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return 0;
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}
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IRQCHIP_DECLARE(ti_wakeupgen, "ti,omap4-wugen-mpu", wakeupgen_init);
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