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88bbe85dcd
In order to easily provide SMP for BCM2837 on 32-bit and 64-bit
the SMP startup code was placed in irq-bcm2836. That's not the
right approach. So move this code where it belongs.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Fixes: 41f4988cc2 ("irqchip/bcm2836: Add SMP support for the 2836")
Tested-by: Eric Anholt <eric@anholt.net>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
71 lines
2.3 KiB
C
71 lines
2.3 KiB
C
/*
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* Root interrupt controller for the BCM2836 (Raspberry Pi 2).
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*
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* Copyright 2015 Broadcom
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define LOCAL_CONTROL 0x000
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#define LOCAL_PRESCALER 0x008
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/*
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* The low 2 bits identify the CPU that the GPU IRQ goes to, and the
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* next 2 bits identify the CPU that the GPU FIQ goes to.
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*/
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#define LOCAL_GPU_ROUTING 0x00c
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/* When setting bits 0-3, enables PMU interrupts on that CPU. */
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#define LOCAL_PM_ROUTING_SET 0x010
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/* When setting bits 0-3, disables PMU interrupts on that CPU. */
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#define LOCAL_PM_ROUTING_CLR 0x014
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/*
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* The low 4 bits of this are the CPU's timer IRQ enables, and the
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* next 4 bits are the CPU's timer FIQ enables (which override the IRQ
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* bits).
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*/
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#define LOCAL_TIMER_INT_CONTROL0 0x040
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/*
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* The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
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* the next 4 bits are the CPU's per-mailbox FIQ enables (which
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* override the IRQ bits).
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*/
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#define LOCAL_MAILBOX_INT_CONTROL0 0x050
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/*
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* The CPU's interrupt status register. Bits are defined by the the
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* LOCAL_IRQ_* bits below.
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*/
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#define LOCAL_IRQ_PENDING0 0x060
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/* Same status bits as above, but for FIQ. */
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#define LOCAL_FIQ_PENDING0 0x070
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/*
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* Mailbox write-to-set bits. There are 16 mailboxes, 4 per CPU, and
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* these bits are organized by mailbox number and then CPU number. We
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* use mailbox 0 for IPIs. The mailbox's interrupt is raised while
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* any bit is set.
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*/
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#define LOCAL_MAILBOX0_SET0 0x080
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#define LOCAL_MAILBOX3_SET0 0x08c
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/* Mailbox write-to-clear bits. */
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#define LOCAL_MAILBOX0_CLR0 0x0c0
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#define LOCAL_MAILBOX3_CLR0 0x0cc
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#define LOCAL_IRQ_CNTPSIRQ 0
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#define LOCAL_IRQ_CNTPNSIRQ 1
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#define LOCAL_IRQ_CNTHPIRQ 2
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#define LOCAL_IRQ_CNTVIRQ 3
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#define LOCAL_IRQ_MAILBOX0 4
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#define LOCAL_IRQ_MAILBOX1 5
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#define LOCAL_IRQ_MAILBOX2 6
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#define LOCAL_IRQ_MAILBOX3 7
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#define LOCAL_IRQ_GPU_FAST 8
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#define LOCAL_IRQ_PMU_FAST 9
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#define LAST_IRQ LOCAL_IRQ_PMU_FAST
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