mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-14 12:26:45 +07:00
eb3d3ec567
Pull ARM updates from Russell King: - Major clean-up of the L2 cache support code. The existing mess was becoming rather unmaintainable through all the additions that others have done over time. This turns it into a much nicer structure, and implements a few performance improvements as well. - Clean up some of the CP15 control register tweaks for alignment support, moving some code and data into alignment.c - DMA properties for ARM, from Santosh and reviewed by DT people. This adds DT properties to specify bus translations we can't discover automatically, and to indicate whether devices are coherent. - Hibernation support for ARM - Make ftrace work with read-only text in modules - add suspend support for PJ4B CPUs - rework interrupt masking for undefined instruction handling, which allows us to enable interrupts earlier in the handling of these exceptions. - support for big endian page tables - fix stacktrace support to exclude stacktrace functions from the trace, and add save_stack_trace_regs() implementation so that kprobes can record stack traces. - Add support for the Cortex-A17 CPU. - Remove last vestiges of ARM710 support. - Removal of ARM "meminfo" structure, finally converting us solely to memblock to handle the early memory initialisation. * 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (142 commits) ARM: ensure C page table setup code follows assembly code (part II) ARM: ensure C page table setup code follows assembly code ARM: consolidate last remaining open-coded alignment trap enable ARM: remove global cr_no_alignment ARM: remove CPU_CP15 conditional from alignment.c ARM: remove unused adjust_cr() function ARM: move "noalign" command line option to alignment.c ARM: provide common method to clear bits in CPU control register ARM: 8025/1: Get rid of meminfo ARM: 8060/1: mm: allow sub-architectures to override PCI I/O memory type ARM: 8066/1: correction for ARM patch 8031/2 ARM: 8049/1: ftrace/add save_stack_trace_regs() implementation ARM: 8065/1: remove last use of CONFIG_CPU_ARM710 ARM: 8062/1: Modify ldrt fixup handler to re-execute the userspace instruction ARM: 8047/1: rwsem: use asm-generic rwsem implementation ARM: l2c: trial at enabling some Cortex-A9 optimisations ARM: l2c: add warnings for stuff modifying aux_ctrl register values ARM: l2c: print a warning with L2C-310 caches if the cache size is modified ARM: l2c: remove old .set_debug method ARM: l2c: kill L2X0_AUX_CTRL_MASK before anyone else makes use of this ...
87 lines
2.6 KiB
C
87 lines
2.6 KiB
C
#ifndef __ARCH_ORION5X_COMMON_H
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#define __ARCH_ORION5X_COMMON_H
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#include <linux/reboot.h>
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struct dsa_platform_data;
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struct mv643xx_eth_platform_data;
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struct mv_sata_platform_data;
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#define ORION_MBUS_PCIE_MEM_TARGET 0x04
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#define ORION_MBUS_PCIE_MEM_ATTR 0x59
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#define ORION_MBUS_PCIE_IO_TARGET 0x04
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#define ORION_MBUS_PCIE_IO_ATTR 0x51
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#define ORION_MBUS_PCIE_WA_TARGET 0x04
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#define ORION_MBUS_PCIE_WA_ATTR 0x79
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#define ORION_MBUS_PCI_MEM_TARGET 0x03
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#define ORION_MBUS_PCI_MEM_ATTR 0x59
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#define ORION_MBUS_PCI_IO_TARGET 0x03
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#define ORION_MBUS_PCI_IO_ATTR 0x51
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#define ORION_MBUS_DEVBUS_BOOT_TARGET 0x01
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#define ORION_MBUS_DEVBUS_BOOT_ATTR 0x0f
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#define ORION_MBUS_DEVBUS_TARGET(cs) 0x01
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#define ORION_MBUS_DEVBUS_ATTR(cs) (~(1 << cs))
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#define ORION_MBUS_SRAM_TARGET 0x09
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#define ORION_MBUS_SRAM_ATTR 0x00
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/*
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* Basic Orion init functions used early by machine-setup.
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*/
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void orion5x_map_io(void);
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void orion5x_init_early(void);
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void orion5x_init_irq(void);
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void orion5x_init(void);
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void orion5x_id(u32 *dev, u32 *rev, char **dev_name);
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void clk_init(void);
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extern int orion5x_tclk;
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extern void orion5x_timer_init(void);
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void orion5x_setup_wins(void);
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void orion5x_ehci0_init(void);
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void orion5x_ehci1_init(void);
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void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data);
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void orion5x_eth_switch_init(struct dsa_platform_data *d, int irq);
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void orion5x_i2c_init(void);
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void orion5x_sata_init(struct mv_sata_platform_data *sata_data);
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void orion5x_spi_init(void);
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void orion5x_uart0_init(void);
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void orion5x_uart1_init(void);
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void orion5x_xor_init(void);
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void orion5x_restart(enum reboot_mode, const char *);
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/*
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* PCIe/PCI functions.
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*/
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struct pci_bus;
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struct pci_sys_data;
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struct pci_dev;
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void orion5x_pcie_id(u32 *dev, u32 *rev);
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void orion5x_pci_disable(void);
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void orion5x_pci_set_cardbus_mode(void);
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int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys);
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struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
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int orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
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struct tag;
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extern void __init tag_fixup_mem32(struct tag *, char **);
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#ifdef CONFIG_MACH_MSS2_DT
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extern void mss2_init(void);
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#else
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static inline void mss2_init(void) {}
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#endif
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/*****************************************************************************
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* Helpers to access Orion registers
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****************************************************************************/
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/*
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* These are not preempt-safe. Locks, if needed, must be taken
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* care of by the caller.
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*/
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#define orion5x_setbits(r, mask) writel(readl(r) | (mask), (r))
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#define orion5x_clrbits(r, mask) writel(readl(r) & ~(mask), (r))
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#endif
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