mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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6fec27d80f
Add emulation for 0x66 prefixed instruction of 0f 28 opcode that has been added earlier. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
4837 lines
123 KiB
C
4837 lines
123 KiB
C
/******************************************************************************
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* emulate.c
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*
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* Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
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*
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* Copyright (c) 2005 Keir Fraser
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*
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* Linux coding style, mod r/m decoder, segment base fixes, real-mode
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* privileged instructions:
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*
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* Copyright (C) 2006 Qumranet
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* Copyright 2010 Red Hat, Inc. and/or its affiliates.
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*
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* Avi Kivity <avi@qumranet.com>
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* Yaniv Kamay <yaniv@qumranet.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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* From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
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*/
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#include <linux/kvm_host.h>
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#include "kvm_cache_regs.h"
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#include <linux/module.h>
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#include <asm/kvm_emulate.h>
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#include <linux/stringify.h>
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#include "x86.h"
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#include "tss.h"
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/*
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* Operand types
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*/
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#define OpNone 0ull
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#define OpImplicit 1ull /* No generic decode */
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#define OpReg 2ull /* Register */
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#define OpMem 3ull /* Memory */
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#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
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#define OpDI 5ull /* ES:DI/EDI/RDI */
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#define OpMem64 6ull /* Memory, 64-bit */
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#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
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#define OpDX 8ull /* DX register */
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#define OpCL 9ull /* CL register (for shifts) */
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#define OpImmByte 10ull /* 8-bit sign extended immediate */
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#define OpOne 11ull /* Implied 1 */
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#define OpImm 12ull /* Sign extended up to 32-bit immediate */
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#define OpMem16 13ull /* Memory operand (16-bit). */
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#define OpMem32 14ull /* Memory operand (32-bit). */
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#define OpImmU 15ull /* Immediate operand, zero extended */
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#define OpSI 16ull /* SI/ESI/RSI */
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#define OpImmFAddr 17ull /* Immediate far address */
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#define OpMemFAddr 18ull /* Far address in memory */
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#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
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#define OpES 20ull /* ES */
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#define OpCS 21ull /* CS */
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#define OpSS 22ull /* SS */
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#define OpDS 23ull /* DS */
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#define OpFS 24ull /* FS */
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#define OpGS 25ull /* GS */
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#define OpMem8 26ull /* 8-bit zero extended memory operand */
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#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
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#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
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#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
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#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
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#define OpBits 5 /* Width of operand field */
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#define OpMask ((1ull << OpBits) - 1)
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/*
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* Opcode effective-address decode tables.
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* Note that we only emulate instructions that have at least one memory
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* operand (excluding implicit stack references). We assume that stack
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* references and instruction fetches will never occur in special memory
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* areas that require emulation. So, for example, 'mov <imm>,<reg>' need
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* not be handled.
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*/
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/* Operand sizes: 8-bit operands or specified/overridden size. */
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#define ByteOp (1<<0) /* 8-bit operands. */
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/* Destination operand type. */
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#define DstShift 1
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#define ImplicitOps (OpImplicit << DstShift)
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#define DstReg (OpReg << DstShift)
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#define DstMem (OpMem << DstShift)
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#define DstAcc (OpAcc << DstShift)
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#define DstDI (OpDI << DstShift)
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#define DstMem64 (OpMem64 << DstShift)
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#define DstImmUByte (OpImmUByte << DstShift)
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#define DstDX (OpDX << DstShift)
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#define DstAccLo (OpAccLo << DstShift)
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#define DstMask (OpMask << DstShift)
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/* Source operand type. */
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#define SrcShift 6
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#define SrcNone (OpNone << SrcShift)
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#define SrcReg (OpReg << SrcShift)
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#define SrcMem (OpMem << SrcShift)
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#define SrcMem16 (OpMem16 << SrcShift)
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#define SrcMem32 (OpMem32 << SrcShift)
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#define SrcImm (OpImm << SrcShift)
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#define SrcImmByte (OpImmByte << SrcShift)
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#define SrcOne (OpOne << SrcShift)
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#define SrcImmUByte (OpImmUByte << SrcShift)
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#define SrcImmU (OpImmU << SrcShift)
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#define SrcSI (OpSI << SrcShift)
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#define SrcXLat (OpXLat << SrcShift)
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#define SrcImmFAddr (OpImmFAddr << SrcShift)
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#define SrcMemFAddr (OpMemFAddr << SrcShift)
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#define SrcAcc (OpAcc << SrcShift)
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#define SrcImmU16 (OpImmU16 << SrcShift)
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#define SrcImm64 (OpImm64 << SrcShift)
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#define SrcDX (OpDX << SrcShift)
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#define SrcMem8 (OpMem8 << SrcShift)
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#define SrcAccHi (OpAccHi << SrcShift)
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#define SrcMask (OpMask << SrcShift)
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#define BitOp (1<<11)
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#define MemAbs (1<<12) /* Memory operand is absolute displacement */
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#define String (1<<13) /* String instruction (rep capable) */
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#define Stack (1<<14) /* Stack instruction (push/pop) */
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#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
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#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
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#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
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#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
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#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
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#define Escape (5<<15) /* Escape to coprocessor instruction */
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#define Sse (1<<18) /* SSE Vector instruction */
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/* Generic ModRM decode. */
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#define ModRM (1<<19)
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/* Destination is only written; never read. */
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#define Mov (1<<20)
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/* Misc flags */
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#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
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#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
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#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
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#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
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#define Undefined (1<<25) /* No Such Instruction */
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#define Lock (1<<26) /* lock prefix is allowed for the instruction */
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#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
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#define No64 (1<<28)
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#define PageTable (1 << 29) /* instruction used to write page table */
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#define NotImpl (1 << 30) /* instruction is not implemented */
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/* Source 2 operand type */
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#define Src2Shift (31)
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#define Src2None (OpNone << Src2Shift)
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#define Src2Mem (OpMem << Src2Shift)
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#define Src2CL (OpCL << Src2Shift)
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#define Src2ImmByte (OpImmByte << Src2Shift)
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#define Src2One (OpOne << Src2Shift)
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#define Src2Imm (OpImm << Src2Shift)
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#define Src2ES (OpES << Src2Shift)
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#define Src2CS (OpCS << Src2Shift)
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#define Src2SS (OpSS << Src2Shift)
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#define Src2DS (OpDS << Src2Shift)
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#define Src2FS (OpFS << Src2Shift)
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#define Src2GS (OpGS << Src2Shift)
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#define Src2Mask (OpMask << Src2Shift)
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#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
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#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
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#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
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#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
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#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
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#define NoWrite ((u64)1 << 45) /* No writeback */
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#define SrcWrite ((u64)1 << 46) /* Write back src operand */
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#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
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#define X2(x...) x, x
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#define X3(x...) X2(x), x
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#define X4(x...) X2(x), X2(x)
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#define X5(x...) X4(x), x
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#define X6(x...) X4(x), X2(x)
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#define X7(x...) X4(x), X3(x)
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#define X8(x...) X4(x), X4(x)
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#define X16(x...) X8(x), X8(x)
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#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
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#define FASTOP_SIZE 8
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/*
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* fastop functions have a special calling convention:
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*
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* dst: rax (in/out)
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* src: rdx (in/out)
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* src2: rcx (in)
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* flags: rflags (in/out)
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* ex: rsi (in:fastop pointer, out:zero if exception)
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*
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* Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
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* different operand sizes can be reached by calculation, rather than a jump
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* table (which would be bigger than the code).
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*
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* fastop functions are declared as taking a never-defined fastop parameter,
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* so they can't be called from C directly.
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*/
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struct fastop;
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struct opcode {
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u64 flags : 56;
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u64 intercept : 8;
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union {
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int (*execute)(struct x86_emulate_ctxt *ctxt);
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const struct opcode *group;
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const struct group_dual *gdual;
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const struct gprefix *gprefix;
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const struct escape *esc;
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void (*fastop)(struct fastop *fake);
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} u;
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int (*check_perm)(struct x86_emulate_ctxt *ctxt);
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};
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struct group_dual {
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struct opcode mod012[8];
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struct opcode mod3[8];
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};
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struct gprefix {
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struct opcode pfx_no;
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struct opcode pfx_66;
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struct opcode pfx_f2;
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struct opcode pfx_f3;
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};
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struct escape {
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struct opcode op[8];
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struct opcode high[64];
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};
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/* EFLAGS bit definitions. */
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#define EFLG_ID (1<<21)
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#define EFLG_VIP (1<<20)
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#define EFLG_VIF (1<<19)
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#define EFLG_AC (1<<18)
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#define EFLG_VM (1<<17)
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#define EFLG_RF (1<<16)
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#define EFLG_IOPL (3<<12)
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#define EFLG_NT (1<<14)
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#define EFLG_OF (1<<11)
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#define EFLG_DF (1<<10)
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#define EFLG_IF (1<<9)
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#define EFLG_TF (1<<8)
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#define EFLG_SF (1<<7)
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#define EFLG_ZF (1<<6)
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#define EFLG_AF (1<<4)
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#define EFLG_PF (1<<2)
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#define EFLG_CF (1<<0)
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#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
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#define EFLG_RESERVED_ONE_MASK 2
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static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
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{
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if (!(ctxt->regs_valid & (1 << nr))) {
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ctxt->regs_valid |= 1 << nr;
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ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
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}
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return ctxt->_regs[nr];
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}
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static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
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{
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ctxt->regs_valid |= 1 << nr;
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ctxt->regs_dirty |= 1 << nr;
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return &ctxt->_regs[nr];
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}
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static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
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{
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reg_read(ctxt, nr);
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return reg_write(ctxt, nr);
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}
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static void writeback_registers(struct x86_emulate_ctxt *ctxt)
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{
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unsigned reg;
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for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
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ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
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}
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static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
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{
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ctxt->regs_dirty = 0;
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ctxt->regs_valid = 0;
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}
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/*
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* These EFLAGS bits are restored from saved value during emulation, and
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* any changes are written back to the saved value after emulation.
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*/
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#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
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#ifdef CONFIG_X86_64
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#define ON64(x) x
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#else
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#define ON64(x)
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#endif
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static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
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#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
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#define FOP_RET "ret \n\t"
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#define FOP_START(op) \
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extern void em_##op(struct fastop *fake); \
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asm(".pushsection .text, \"ax\" \n\t" \
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".global em_" #op " \n\t" \
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FOP_ALIGN \
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"em_" #op ": \n\t"
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#define FOP_END \
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".popsection")
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#define FOPNOP() FOP_ALIGN FOP_RET
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#define FOP1E(op, dst) \
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FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
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#define FOP1EEX(op, dst) \
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FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
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#define FASTOP1(op) \
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FOP_START(op) \
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FOP1E(op##b, al) \
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FOP1E(op##w, ax) \
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FOP1E(op##l, eax) \
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ON64(FOP1E(op##q, rax)) \
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FOP_END
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/* 1-operand, using src2 (for MUL/DIV r/m) */
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#define FASTOP1SRC2(op, name) \
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FOP_START(name) \
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FOP1E(op, cl) \
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FOP1E(op, cx) \
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FOP1E(op, ecx) \
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ON64(FOP1E(op, rcx)) \
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FOP_END
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/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
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#define FASTOP1SRC2EX(op, name) \
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FOP_START(name) \
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FOP1EEX(op, cl) \
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FOP1EEX(op, cx) \
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FOP1EEX(op, ecx) \
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ON64(FOP1EEX(op, rcx)) \
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FOP_END
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#define FOP2E(op, dst, src) \
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FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
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#define FASTOP2(op) \
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FOP_START(op) \
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FOP2E(op##b, al, dl) \
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FOP2E(op##w, ax, dx) \
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FOP2E(op##l, eax, edx) \
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ON64(FOP2E(op##q, rax, rdx)) \
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FOP_END
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/* 2 operand, word only */
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#define FASTOP2W(op) \
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FOP_START(op) \
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FOPNOP() \
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FOP2E(op##w, ax, dx) \
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FOP2E(op##l, eax, edx) \
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ON64(FOP2E(op##q, rax, rdx)) \
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FOP_END
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/* 2 operand, src is CL */
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#define FASTOP2CL(op) \
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FOP_START(op) \
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FOP2E(op##b, al, cl) \
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FOP2E(op##w, ax, cl) \
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FOP2E(op##l, eax, cl) \
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ON64(FOP2E(op##q, rax, cl)) \
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FOP_END
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#define FOP3E(op, dst, src, src2) \
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FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
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/* 3-operand, word-only, src2=cl */
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#define FASTOP3WCL(op) \
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FOP_START(op) \
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FOPNOP() \
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FOP3E(op##w, ax, dx, cl) \
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FOP3E(op##l, eax, edx, cl) \
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ON64(FOP3E(op##q, rax, rdx, cl)) \
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FOP_END
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/* Special case for SETcc - 1 instruction per cc */
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#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
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asm(".global kvm_fastop_exception \n"
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"kvm_fastop_exception: xor %esi, %esi; ret");
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FOP_START(setcc)
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FOP_SETCC(seto)
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FOP_SETCC(setno)
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FOP_SETCC(setc)
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FOP_SETCC(setnc)
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FOP_SETCC(setz)
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FOP_SETCC(setnz)
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FOP_SETCC(setbe)
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FOP_SETCC(setnbe)
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FOP_SETCC(sets)
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FOP_SETCC(setns)
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FOP_SETCC(setp)
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FOP_SETCC(setnp)
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FOP_SETCC(setl)
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FOP_SETCC(setnl)
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FOP_SETCC(setle)
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FOP_SETCC(setnle)
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FOP_END;
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FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
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FOP_END;
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static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
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enum x86_intercept intercept,
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enum x86_intercept_stage stage)
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{
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struct x86_instruction_info info = {
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.intercept = intercept,
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.rep_prefix = ctxt->rep_prefix,
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.modrm_mod = ctxt->modrm_mod,
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.modrm_reg = ctxt->modrm_reg,
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.modrm_rm = ctxt->modrm_rm,
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.src_val = ctxt->src.val64,
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.src_bytes = ctxt->src.bytes,
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.dst_bytes = ctxt->dst.bytes,
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.ad_bytes = ctxt->ad_bytes,
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.next_rip = ctxt->eip,
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};
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return ctxt->ops->intercept(ctxt, &info, stage);
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|
}
|
|
|
|
static void assign_masked(ulong *dest, ulong src, ulong mask)
|
|
{
|
|
*dest = (*dest & ~mask) | (src & mask);
|
|
}
|
|
|
|
static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
return (1UL << (ctxt->ad_bytes << 3)) - 1;
|
|
}
|
|
|
|
static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u16 sel;
|
|
struct desc_struct ss;
|
|
|
|
if (ctxt->mode == X86EMUL_MODE_PROT64)
|
|
return ~0UL;
|
|
ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
|
|
return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
|
|
}
|
|
|
|
static int stack_size(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
return (__fls(stack_mask(ctxt)) + 1) >> 3;
|
|
}
|
|
|
|
/* Access/update address held in a register, based on addressing mode. */
|
|
static inline unsigned long
|
|
address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
|
|
{
|
|
if (ctxt->ad_bytes == sizeof(unsigned long))
|
|
return reg;
|
|
else
|
|
return reg & ad_mask(ctxt);
|
|
}
|
|
|
|
static inline unsigned long
|
|
register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
|
|
{
|
|
return address_mask(ctxt, reg);
|
|
}
|
|
|
|
static void masked_increment(ulong *reg, ulong mask, int inc)
|
|
{
|
|
assign_masked(reg, *reg + inc, mask);
|
|
}
|
|
|
|
static inline void
|
|
register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
|
|
{
|
|
ulong mask;
|
|
|
|
if (ctxt->ad_bytes == sizeof(unsigned long))
|
|
mask = ~0UL;
|
|
else
|
|
mask = ad_mask(ctxt);
|
|
masked_increment(reg, mask, inc);
|
|
}
|
|
|
|
static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
|
|
{
|
|
masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
|
|
}
|
|
|
|
static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
|
|
{
|
|
register_address_increment(ctxt, &ctxt->_eip, rel);
|
|
}
|
|
|
|
static u32 desc_limit_scaled(struct desc_struct *desc)
|
|
{
|
|
u32 limit = get_desc_limit(desc);
|
|
|
|
return desc->g ? (limit << 12) | 0xfff : limit;
|
|
}
|
|
|
|
static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
|
|
{
|
|
ctxt->has_seg_override = true;
|
|
ctxt->seg_override = seg;
|
|
}
|
|
|
|
static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
|
|
{
|
|
if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
|
|
return 0;
|
|
|
|
return ctxt->ops->get_cached_segment_base(ctxt, seg);
|
|
}
|
|
|
|
static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
if (!ctxt->has_seg_override)
|
|
return 0;
|
|
|
|
return ctxt->seg_override;
|
|
}
|
|
|
|
static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
|
|
u32 error, bool valid)
|
|
{
|
|
ctxt->exception.vector = vec;
|
|
ctxt->exception.error_code = error;
|
|
ctxt->exception.error_code_valid = valid;
|
|
return X86EMUL_PROPAGATE_FAULT;
|
|
}
|
|
|
|
static int emulate_db(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
return emulate_exception(ctxt, DB_VECTOR, 0, false);
|
|
}
|
|
|
|
static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
|
|
{
|
|
return emulate_exception(ctxt, GP_VECTOR, err, true);
|
|
}
|
|
|
|
static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
|
|
{
|
|
return emulate_exception(ctxt, SS_VECTOR, err, true);
|
|
}
|
|
|
|
static int emulate_ud(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
return emulate_exception(ctxt, UD_VECTOR, 0, false);
|
|
}
|
|
|
|
static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
|
|
{
|
|
return emulate_exception(ctxt, TS_VECTOR, err, true);
|
|
}
|
|
|
|
static int emulate_de(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
return emulate_exception(ctxt, DE_VECTOR, 0, false);
|
|
}
|
|
|
|
static int emulate_nm(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
return emulate_exception(ctxt, NM_VECTOR, 0, false);
|
|
}
|
|
|
|
static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
|
|
{
|
|
u16 selector;
|
|
struct desc_struct desc;
|
|
|
|
ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
|
|
return selector;
|
|
}
|
|
|
|
static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
|
|
unsigned seg)
|
|
{
|
|
u16 dummy;
|
|
u32 base3;
|
|
struct desc_struct desc;
|
|
|
|
ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
|
|
ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
|
|
}
|
|
|
|
/*
|
|
* x86 defines three classes of vector instructions: explicitly
|
|
* aligned, explicitly unaligned, and the rest, which change behaviour
|
|
* depending on whether they're AVX encoded or not.
|
|
*
|
|
* Also included is CMPXCHG16B which is not a vector instruction, yet it is
|
|
* subject to the same check.
|
|
*/
|
|
static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
|
|
{
|
|
if (likely(size < 16))
|
|
return false;
|
|
|
|
if (ctxt->d & Aligned)
|
|
return true;
|
|
else if (ctxt->d & Unaligned)
|
|
return false;
|
|
else if (ctxt->d & Avx)
|
|
return false;
|
|
else
|
|
return true;
|
|
}
|
|
|
|
static int __linearize(struct x86_emulate_ctxt *ctxt,
|
|
struct segmented_address addr,
|
|
unsigned size, bool write, bool fetch,
|
|
ulong *linear)
|
|
{
|
|
struct desc_struct desc;
|
|
bool usable;
|
|
ulong la;
|
|
u32 lim;
|
|
u16 sel;
|
|
unsigned cpl;
|
|
|
|
la = seg_base(ctxt, addr.seg) + addr.ea;
|
|
switch (ctxt->mode) {
|
|
case X86EMUL_MODE_PROT64:
|
|
if (((signed long)la << 16) >> 16 != la)
|
|
return emulate_gp(ctxt, 0);
|
|
break;
|
|
default:
|
|
usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
|
|
addr.seg);
|
|
if (!usable)
|
|
goto bad;
|
|
/* code segment in protected mode or read-only data segment */
|
|
if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
|
|
|| !(desc.type & 2)) && write)
|
|
goto bad;
|
|
/* unreadable code segment */
|
|
if (!fetch && (desc.type & 8) && !(desc.type & 2))
|
|
goto bad;
|
|
lim = desc_limit_scaled(&desc);
|
|
if ((desc.type & 8) || !(desc.type & 4)) {
|
|
/* expand-up segment */
|
|
if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
|
|
goto bad;
|
|
} else {
|
|
/* expand-down segment */
|
|
if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
|
|
goto bad;
|
|
lim = desc.d ? 0xffffffff : 0xffff;
|
|
if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
|
|
goto bad;
|
|
}
|
|
cpl = ctxt->ops->cpl(ctxt);
|
|
if (!(desc.type & 8)) {
|
|
/* data segment */
|
|
if (cpl > desc.dpl)
|
|
goto bad;
|
|
} else if ((desc.type & 8) && !(desc.type & 4)) {
|
|
/* nonconforming code segment */
|
|
if (cpl != desc.dpl)
|
|
goto bad;
|
|
} else if ((desc.type & 8) && (desc.type & 4)) {
|
|
/* conforming code segment */
|
|
if (cpl < desc.dpl)
|
|
goto bad;
|
|
}
|
|
break;
|
|
}
|
|
if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
|
|
la &= (u32)-1;
|
|
if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
|
|
return emulate_gp(ctxt, 0);
|
|
*linear = la;
|
|
return X86EMUL_CONTINUE;
|
|
bad:
|
|
if (addr.seg == VCPU_SREG_SS)
|
|
return emulate_ss(ctxt, sel);
|
|
else
|
|
return emulate_gp(ctxt, sel);
|
|
}
|
|
|
|
static int linearize(struct x86_emulate_ctxt *ctxt,
|
|
struct segmented_address addr,
|
|
unsigned size, bool write,
|
|
ulong *linear)
|
|
{
|
|
return __linearize(ctxt, addr, size, write, false, linear);
|
|
}
|
|
|
|
|
|
static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
|
|
struct segmented_address addr,
|
|
void *data,
|
|
unsigned size)
|
|
{
|
|
int rc;
|
|
ulong linear;
|
|
|
|
rc = linearize(ctxt, addr, size, false, &linear);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
|
|
}
|
|
|
|
/*
|
|
* Fetch the next byte of the instruction being emulated which is pointed to
|
|
* by ctxt->_eip, then increment ctxt->_eip.
|
|
*
|
|
* Also prefetch the remaining bytes of the instruction without crossing page
|
|
* boundary if they are not in fetch_cache yet.
|
|
*/
|
|
static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
|
|
{
|
|
struct fetch_cache *fc = &ctxt->fetch;
|
|
int rc;
|
|
int size, cur_size;
|
|
|
|
if (ctxt->_eip == fc->end) {
|
|
unsigned long linear;
|
|
struct segmented_address addr = { .seg = VCPU_SREG_CS,
|
|
.ea = ctxt->_eip };
|
|
cur_size = fc->end - fc->start;
|
|
size = min(15UL - cur_size,
|
|
PAGE_SIZE - offset_in_page(ctxt->_eip));
|
|
rc = __linearize(ctxt, addr, size, false, true, &linear);
|
|
if (unlikely(rc != X86EMUL_CONTINUE))
|
|
return rc;
|
|
rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
|
|
size, &ctxt->exception);
|
|
if (unlikely(rc != X86EMUL_CONTINUE))
|
|
return rc;
|
|
fc->end += size;
|
|
}
|
|
*dest = fc->data[ctxt->_eip - fc->start];
|
|
ctxt->_eip++;
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
|
|
void *dest, unsigned size)
|
|
{
|
|
int rc;
|
|
|
|
/* x86 instructions are limited to 15 bytes. */
|
|
if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
|
|
return X86EMUL_UNHANDLEABLE;
|
|
while (size--) {
|
|
rc = do_insn_fetch_byte(ctxt, dest++);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
}
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
/* Fetch next part of the instruction being emulated. */
|
|
#define insn_fetch(_type, _ctxt) \
|
|
({ unsigned long _x; \
|
|
rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
|
|
if (rc != X86EMUL_CONTINUE) \
|
|
goto done; \
|
|
(_type)_x; \
|
|
})
|
|
|
|
#define insn_fetch_arr(_arr, _size, _ctxt) \
|
|
({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
|
|
if (rc != X86EMUL_CONTINUE) \
|
|
goto done; \
|
|
})
|
|
|
|
/*
|
|
* Given the 'reg' portion of a ModRM byte, and a register block, return a
|
|
* pointer into the block that addresses the relevant register.
|
|
* @highbyte_regs specifies whether to decode AH,CH,DH,BH.
|
|
*/
|
|
static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
|
|
int byteop)
|
|
{
|
|
void *p;
|
|
int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
|
|
|
|
if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
|
|
p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
|
|
else
|
|
p = reg_rmw(ctxt, modrm_reg);
|
|
return p;
|
|
}
|
|
|
|
static int read_descriptor(struct x86_emulate_ctxt *ctxt,
|
|
struct segmented_address addr,
|
|
u16 *size, unsigned long *address, int op_bytes)
|
|
{
|
|
int rc;
|
|
|
|
if (op_bytes == 2)
|
|
op_bytes = 3;
|
|
*address = 0;
|
|
rc = segmented_read_std(ctxt, addr, size, 2);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
addr.ea += 2;
|
|
rc = segmented_read_std(ctxt, addr, address, op_bytes);
|
|
return rc;
|
|
}
|
|
|
|
FASTOP2(add);
|
|
FASTOP2(or);
|
|
FASTOP2(adc);
|
|
FASTOP2(sbb);
|
|
FASTOP2(and);
|
|
FASTOP2(sub);
|
|
FASTOP2(xor);
|
|
FASTOP2(cmp);
|
|
FASTOP2(test);
|
|
|
|
FASTOP1SRC2(mul, mul_ex);
|
|
FASTOP1SRC2(imul, imul_ex);
|
|
FASTOP1SRC2EX(div, div_ex);
|
|
FASTOP1SRC2EX(idiv, idiv_ex);
|
|
|
|
FASTOP3WCL(shld);
|
|
FASTOP3WCL(shrd);
|
|
|
|
FASTOP2W(imul);
|
|
|
|
FASTOP1(not);
|
|
FASTOP1(neg);
|
|
FASTOP1(inc);
|
|
FASTOP1(dec);
|
|
|
|
FASTOP2CL(rol);
|
|
FASTOP2CL(ror);
|
|
FASTOP2CL(rcl);
|
|
FASTOP2CL(rcr);
|
|
FASTOP2CL(shl);
|
|
FASTOP2CL(shr);
|
|
FASTOP2CL(sar);
|
|
|
|
FASTOP2W(bsf);
|
|
FASTOP2W(bsr);
|
|
FASTOP2W(bt);
|
|
FASTOP2W(bts);
|
|
FASTOP2W(btr);
|
|
FASTOP2W(btc);
|
|
|
|
FASTOP2(xadd);
|
|
|
|
static u8 test_cc(unsigned int condition, unsigned long flags)
|
|
{
|
|
u8 rc;
|
|
void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
|
|
|
|
flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
|
|
asm("push %[flags]; popf; call *%[fastop]"
|
|
: "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
|
|
return rc;
|
|
}
|
|
|
|
static void fetch_register_operand(struct operand *op)
|
|
{
|
|
switch (op->bytes) {
|
|
case 1:
|
|
op->val = *(u8 *)op->addr.reg;
|
|
break;
|
|
case 2:
|
|
op->val = *(u16 *)op->addr.reg;
|
|
break;
|
|
case 4:
|
|
op->val = *(u32 *)op->addr.reg;
|
|
break;
|
|
case 8:
|
|
op->val = *(u64 *)op->addr.reg;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
|
|
{
|
|
ctxt->ops->get_fpu(ctxt);
|
|
switch (reg) {
|
|
case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
|
|
case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
|
|
case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
|
|
case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
|
|
case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
|
|
case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
|
|
case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
|
|
case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
|
|
#ifdef CONFIG_X86_64
|
|
case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
|
|
case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
|
|
case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
|
|
case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
|
|
case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
|
|
case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
|
|
case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
|
|
case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
|
|
#endif
|
|
default: BUG();
|
|
}
|
|
ctxt->ops->put_fpu(ctxt);
|
|
}
|
|
|
|
static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
|
|
int reg)
|
|
{
|
|
ctxt->ops->get_fpu(ctxt);
|
|
switch (reg) {
|
|
case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
|
|
case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
|
|
case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
|
|
case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
|
|
case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
|
|
case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
|
|
case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
|
|
case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
|
|
#ifdef CONFIG_X86_64
|
|
case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
|
|
case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
|
|
case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
|
|
case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
|
|
case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
|
|
case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
|
|
case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
|
|
case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
|
|
#endif
|
|
default: BUG();
|
|
}
|
|
ctxt->ops->put_fpu(ctxt);
|
|
}
|
|
|
|
static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
|
|
{
|
|
ctxt->ops->get_fpu(ctxt);
|
|
switch (reg) {
|
|
case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
|
|
case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
|
|
case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
|
|
case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
|
|
case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
|
|
case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
|
|
case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
|
|
case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
|
|
default: BUG();
|
|
}
|
|
ctxt->ops->put_fpu(ctxt);
|
|
}
|
|
|
|
static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
|
|
{
|
|
ctxt->ops->get_fpu(ctxt);
|
|
switch (reg) {
|
|
case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
|
|
case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
|
|
case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
|
|
case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
|
|
case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
|
|
case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
|
|
case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
|
|
case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
|
|
default: BUG();
|
|
}
|
|
ctxt->ops->put_fpu(ctxt);
|
|
}
|
|
|
|
static int em_fninit(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
|
|
return emulate_nm(ctxt);
|
|
|
|
ctxt->ops->get_fpu(ctxt);
|
|
asm volatile("fninit");
|
|
ctxt->ops->put_fpu(ctxt);
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u16 fcw;
|
|
|
|
if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
|
|
return emulate_nm(ctxt);
|
|
|
|
ctxt->ops->get_fpu(ctxt);
|
|
asm volatile("fnstcw %0": "+m"(fcw));
|
|
ctxt->ops->put_fpu(ctxt);
|
|
|
|
/* force 2 byte destination */
|
|
ctxt->dst.bytes = 2;
|
|
ctxt->dst.val = fcw;
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u16 fsw;
|
|
|
|
if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
|
|
return emulate_nm(ctxt);
|
|
|
|
ctxt->ops->get_fpu(ctxt);
|
|
asm volatile("fnstsw %0": "+m"(fsw));
|
|
ctxt->ops->put_fpu(ctxt);
|
|
|
|
/* force 2 byte destination */
|
|
ctxt->dst.bytes = 2;
|
|
ctxt->dst.val = fsw;
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
|
|
struct operand *op)
|
|
{
|
|
unsigned reg = ctxt->modrm_reg;
|
|
|
|
if (!(ctxt->d & ModRM))
|
|
reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
|
|
|
|
if (ctxt->d & Sse) {
|
|
op->type = OP_XMM;
|
|
op->bytes = 16;
|
|
op->addr.xmm = reg;
|
|
read_sse_reg(ctxt, &op->vec_val, reg);
|
|
return;
|
|
}
|
|
if (ctxt->d & Mmx) {
|
|
reg &= 7;
|
|
op->type = OP_MM;
|
|
op->bytes = 8;
|
|
op->addr.mm = reg;
|
|
return;
|
|
}
|
|
|
|
op->type = OP_REG;
|
|
op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
|
|
op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
|
|
|
|
fetch_register_operand(op);
|
|
op->orig_val = op->val;
|
|
}
|
|
|
|
static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
|
|
{
|
|
if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
|
|
ctxt->modrm_seg = VCPU_SREG_SS;
|
|
}
|
|
|
|
static int decode_modrm(struct x86_emulate_ctxt *ctxt,
|
|
struct operand *op)
|
|
{
|
|
u8 sib;
|
|
int index_reg = 0, base_reg = 0, scale;
|
|
int rc = X86EMUL_CONTINUE;
|
|
ulong modrm_ea = 0;
|
|
|
|
if (ctxt->rex_prefix) {
|
|
ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
|
|
index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
|
|
ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
|
|
}
|
|
|
|
ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
|
|
ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
|
|
ctxt->modrm_rm |= (ctxt->modrm & 0x07);
|
|
ctxt->modrm_seg = VCPU_SREG_DS;
|
|
|
|
if (ctxt->modrm_mod == 3) {
|
|
op->type = OP_REG;
|
|
op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
|
|
op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
|
|
ctxt->d & ByteOp);
|
|
if (ctxt->d & Sse) {
|
|
op->type = OP_XMM;
|
|
op->bytes = 16;
|
|
op->addr.xmm = ctxt->modrm_rm;
|
|
read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
|
|
return rc;
|
|
}
|
|
if (ctxt->d & Mmx) {
|
|
op->type = OP_MM;
|
|
op->bytes = 8;
|
|
op->addr.xmm = ctxt->modrm_rm & 7;
|
|
return rc;
|
|
}
|
|
fetch_register_operand(op);
|
|
return rc;
|
|
}
|
|
|
|
op->type = OP_MEM;
|
|
|
|
if (ctxt->ad_bytes == 2) {
|
|
unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
|
|
unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
|
|
unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
|
|
unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
|
|
|
|
/* 16-bit ModR/M decode. */
|
|
switch (ctxt->modrm_mod) {
|
|
case 0:
|
|
if (ctxt->modrm_rm == 6)
|
|
modrm_ea += insn_fetch(u16, ctxt);
|
|
break;
|
|
case 1:
|
|
modrm_ea += insn_fetch(s8, ctxt);
|
|
break;
|
|
case 2:
|
|
modrm_ea += insn_fetch(u16, ctxt);
|
|
break;
|
|
}
|
|
switch (ctxt->modrm_rm) {
|
|
case 0:
|
|
modrm_ea += bx + si;
|
|
break;
|
|
case 1:
|
|
modrm_ea += bx + di;
|
|
break;
|
|
case 2:
|
|
modrm_ea += bp + si;
|
|
break;
|
|
case 3:
|
|
modrm_ea += bp + di;
|
|
break;
|
|
case 4:
|
|
modrm_ea += si;
|
|
break;
|
|
case 5:
|
|
modrm_ea += di;
|
|
break;
|
|
case 6:
|
|
if (ctxt->modrm_mod != 0)
|
|
modrm_ea += bp;
|
|
break;
|
|
case 7:
|
|
modrm_ea += bx;
|
|
break;
|
|
}
|
|
if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
|
|
(ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
|
|
ctxt->modrm_seg = VCPU_SREG_SS;
|
|
modrm_ea = (u16)modrm_ea;
|
|
} else {
|
|
/* 32/64-bit ModR/M decode. */
|
|
if ((ctxt->modrm_rm & 7) == 4) {
|
|
sib = insn_fetch(u8, ctxt);
|
|
index_reg |= (sib >> 3) & 7;
|
|
base_reg |= sib & 7;
|
|
scale = sib >> 6;
|
|
|
|
if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
|
|
modrm_ea += insn_fetch(s32, ctxt);
|
|
else {
|
|
modrm_ea += reg_read(ctxt, base_reg);
|
|
adjust_modrm_seg(ctxt, base_reg);
|
|
}
|
|
if (index_reg != 4)
|
|
modrm_ea += reg_read(ctxt, index_reg) << scale;
|
|
} else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
|
|
if (ctxt->mode == X86EMUL_MODE_PROT64)
|
|
ctxt->rip_relative = 1;
|
|
} else {
|
|
base_reg = ctxt->modrm_rm;
|
|
modrm_ea += reg_read(ctxt, base_reg);
|
|
adjust_modrm_seg(ctxt, base_reg);
|
|
}
|
|
switch (ctxt->modrm_mod) {
|
|
case 0:
|
|
if (ctxt->modrm_rm == 5)
|
|
modrm_ea += insn_fetch(s32, ctxt);
|
|
break;
|
|
case 1:
|
|
modrm_ea += insn_fetch(s8, ctxt);
|
|
break;
|
|
case 2:
|
|
modrm_ea += insn_fetch(s32, ctxt);
|
|
break;
|
|
}
|
|
}
|
|
op->addr.mem.ea = modrm_ea;
|
|
done:
|
|
return rc;
|
|
}
|
|
|
|
static int decode_abs(struct x86_emulate_ctxt *ctxt,
|
|
struct operand *op)
|
|
{
|
|
int rc = X86EMUL_CONTINUE;
|
|
|
|
op->type = OP_MEM;
|
|
switch (ctxt->ad_bytes) {
|
|
case 2:
|
|
op->addr.mem.ea = insn_fetch(u16, ctxt);
|
|
break;
|
|
case 4:
|
|
op->addr.mem.ea = insn_fetch(u32, ctxt);
|
|
break;
|
|
case 8:
|
|
op->addr.mem.ea = insn_fetch(u64, ctxt);
|
|
break;
|
|
}
|
|
done:
|
|
return rc;
|
|
}
|
|
|
|
static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
long sv = 0, mask;
|
|
|
|
if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
|
|
mask = ~(ctxt->dst.bytes * 8 - 1);
|
|
|
|
if (ctxt->src.bytes == 2)
|
|
sv = (s16)ctxt->src.val & (s16)mask;
|
|
else if (ctxt->src.bytes == 4)
|
|
sv = (s32)ctxt->src.val & (s32)mask;
|
|
|
|
ctxt->dst.addr.mem.ea += (sv >> 3);
|
|
}
|
|
|
|
/* only subword offset */
|
|
ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
|
|
}
|
|
|
|
static int read_emulated(struct x86_emulate_ctxt *ctxt,
|
|
unsigned long addr, void *dest, unsigned size)
|
|
{
|
|
int rc;
|
|
struct read_cache *mc = &ctxt->mem_read;
|
|
|
|
if (mc->pos < mc->end)
|
|
goto read_cached;
|
|
|
|
WARN_ON((mc->end + size) >= sizeof(mc->data));
|
|
|
|
rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
|
|
&ctxt->exception);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
|
|
mc->end += size;
|
|
|
|
read_cached:
|
|
memcpy(dest, mc->data + mc->pos, size);
|
|
mc->pos += size;
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int segmented_read(struct x86_emulate_ctxt *ctxt,
|
|
struct segmented_address addr,
|
|
void *data,
|
|
unsigned size)
|
|
{
|
|
int rc;
|
|
ulong linear;
|
|
|
|
rc = linearize(ctxt, addr, size, false, &linear);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
return read_emulated(ctxt, linear, data, size);
|
|
}
|
|
|
|
static int segmented_write(struct x86_emulate_ctxt *ctxt,
|
|
struct segmented_address addr,
|
|
const void *data,
|
|
unsigned size)
|
|
{
|
|
int rc;
|
|
ulong linear;
|
|
|
|
rc = linearize(ctxt, addr, size, true, &linear);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
return ctxt->ops->write_emulated(ctxt, linear, data, size,
|
|
&ctxt->exception);
|
|
}
|
|
|
|
static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
|
|
struct segmented_address addr,
|
|
const void *orig_data, const void *data,
|
|
unsigned size)
|
|
{
|
|
int rc;
|
|
ulong linear;
|
|
|
|
rc = linearize(ctxt, addr, size, true, &linear);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
|
|
size, &ctxt->exception);
|
|
}
|
|
|
|
static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
|
|
unsigned int size, unsigned short port,
|
|
void *dest)
|
|
{
|
|
struct read_cache *rc = &ctxt->io_read;
|
|
|
|
if (rc->pos == rc->end) { /* refill pio read ahead */
|
|
unsigned int in_page, n;
|
|
unsigned int count = ctxt->rep_prefix ?
|
|
address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
|
|
in_page = (ctxt->eflags & EFLG_DF) ?
|
|
offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
|
|
PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
|
|
n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
|
|
count);
|
|
if (n == 0)
|
|
n = 1;
|
|
rc->pos = rc->end = 0;
|
|
if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
|
|
return 0;
|
|
rc->end = n * size;
|
|
}
|
|
|
|
if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) {
|
|
ctxt->dst.data = rc->data + rc->pos;
|
|
ctxt->dst.type = OP_MEM_STR;
|
|
ctxt->dst.count = (rc->end - rc->pos) / size;
|
|
rc->pos = rc->end;
|
|
} else {
|
|
memcpy(dest, rc->data + rc->pos, size);
|
|
rc->pos += size;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
|
|
u16 index, struct desc_struct *desc)
|
|
{
|
|
struct desc_ptr dt;
|
|
ulong addr;
|
|
|
|
ctxt->ops->get_idt(ctxt, &dt);
|
|
|
|
if (dt.size < index * 8 + 7)
|
|
return emulate_gp(ctxt, index << 3 | 0x2);
|
|
|
|
addr = dt.address + index * 8;
|
|
return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
|
|
&ctxt->exception);
|
|
}
|
|
|
|
static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
|
|
u16 selector, struct desc_ptr *dt)
|
|
{
|
|
const struct x86_emulate_ops *ops = ctxt->ops;
|
|
|
|
if (selector & 1 << 2) {
|
|
struct desc_struct desc;
|
|
u16 sel;
|
|
|
|
memset (dt, 0, sizeof *dt);
|
|
if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
|
|
return;
|
|
|
|
dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
|
|
dt->address = get_desc_base(&desc);
|
|
} else
|
|
ops->get_gdt(ctxt, dt);
|
|
}
|
|
|
|
/* allowed just for 8 bytes segments */
|
|
static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
|
|
u16 selector, struct desc_struct *desc,
|
|
ulong *desc_addr_p)
|
|
{
|
|
struct desc_ptr dt;
|
|
u16 index = selector >> 3;
|
|
ulong addr;
|
|
|
|
get_descriptor_table_ptr(ctxt, selector, &dt);
|
|
|
|
if (dt.size < index * 8 + 7)
|
|
return emulate_gp(ctxt, selector & 0xfffc);
|
|
|
|
*desc_addr_p = addr = dt.address + index * 8;
|
|
return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
|
|
&ctxt->exception);
|
|
}
|
|
|
|
/* allowed just for 8 bytes segments */
|
|
static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
|
|
u16 selector, struct desc_struct *desc)
|
|
{
|
|
struct desc_ptr dt;
|
|
u16 index = selector >> 3;
|
|
ulong addr;
|
|
|
|
get_descriptor_table_ptr(ctxt, selector, &dt);
|
|
|
|
if (dt.size < index * 8 + 7)
|
|
return emulate_gp(ctxt, selector & 0xfffc);
|
|
|
|
addr = dt.address + index * 8;
|
|
return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
|
|
&ctxt->exception);
|
|
}
|
|
|
|
/* Does not support long mode */
|
|
static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
|
|
u16 selector, int seg)
|
|
{
|
|
struct desc_struct seg_desc, old_desc;
|
|
u8 dpl, rpl, cpl;
|
|
unsigned err_vec = GP_VECTOR;
|
|
u32 err_code = 0;
|
|
bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
|
|
ulong desc_addr;
|
|
int ret;
|
|
u16 dummy;
|
|
|
|
memset(&seg_desc, 0, sizeof seg_desc);
|
|
|
|
if (ctxt->mode == X86EMUL_MODE_REAL) {
|
|
/* set real mode segment descriptor (keep limit etc. for
|
|
* unreal mode) */
|
|
ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
|
|
set_desc_base(&seg_desc, selector << 4);
|
|
goto load;
|
|
} else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
|
|
/* VM86 needs a clean new segment descriptor */
|
|
set_desc_base(&seg_desc, selector << 4);
|
|
set_desc_limit(&seg_desc, 0xffff);
|
|
seg_desc.type = 3;
|
|
seg_desc.p = 1;
|
|
seg_desc.s = 1;
|
|
seg_desc.dpl = 3;
|
|
goto load;
|
|
}
|
|
|
|
rpl = selector & 3;
|
|
cpl = ctxt->ops->cpl(ctxt);
|
|
|
|
/* NULL selector is not valid for TR, CS and SS (except for long mode) */
|
|
if ((seg == VCPU_SREG_CS
|
|
|| (seg == VCPU_SREG_SS
|
|
&& (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
|
|
|| seg == VCPU_SREG_TR)
|
|
&& null_selector)
|
|
goto exception;
|
|
|
|
/* TR should be in GDT only */
|
|
if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
|
|
goto exception;
|
|
|
|
if (null_selector) /* for NULL selector skip all following checks */
|
|
goto load;
|
|
|
|
ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
return ret;
|
|
|
|
err_code = selector & 0xfffc;
|
|
err_vec = GP_VECTOR;
|
|
|
|
/* can't load system descriptor into segment selector */
|
|
if (seg <= VCPU_SREG_GS && !seg_desc.s)
|
|
goto exception;
|
|
|
|
if (!seg_desc.p) {
|
|
err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
|
|
goto exception;
|
|
}
|
|
|
|
dpl = seg_desc.dpl;
|
|
|
|
switch (seg) {
|
|
case VCPU_SREG_SS:
|
|
/*
|
|
* segment is not a writable data segment or segment
|
|
* selector's RPL != CPL or segment selector's RPL != CPL
|
|
*/
|
|
if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
|
|
goto exception;
|
|
break;
|
|
case VCPU_SREG_CS:
|
|
if (!(seg_desc.type & 8))
|
|
goto exception;
|
|
|
|
if (seg_desc.type & 4) {
|
|
/* conforming */
|
|
if (dpl > cpl)
|
|
goto exception;
|
|
} else {
|
|
/* nonconforming */
|
|
if (rpl > cpl || dpl != cpl)
|
|
goto exception;
|
|
}
|
|
/* CS(RPL) <- CPL */
|
|
selector = (selector & 0xfffc) | cpl;
|
|
break;
|
|
case VCPU_SREG_TR:
|
|
if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
|
|
goto exception;
|
|
old_desc = seg_desc;
|
|
seg_desc.type |= 2; /* busy */
|
|
ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
|
|
sizeof(seg_desc), &ctxt->exception);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
return ret;
|
|
break;
|
|
case VCPU_SREG_LDTR:
|
|
if (seg_desc.s || seg_desc.type != 2)
|
|
goto exception;
|
|
break;
|
|
default: /* DS, ES, FS, or GS */
|
|
/*
|
|
* segment is not a data or readable code segment or
|
|
* ((segment is a data or nonconforming code segment)
|
|
* and (both RPL and CPL > DPL))
|
|
*/
|
|
if ((seg_desc.type & 0xa) == 0x8 ||
|
|
(((seg_desc.type & 0xc) != 0xc) &&
|
|
(rpl > dpl && cpl > dpl)))
|
|
goto exception;
|
|
break;
|
|
}
|
|
|
|
if (seg_desc.s) {
|
|
/* mark segment as accessed */
|
|
seg_desc.type |= 1;
|
|
ret = write_segment_descriptor(ctxt, selector, &seg_desc);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
return ret;
|
|
}
|
|
load:
|
|
ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
|
|
return X86EMUL_CONTINUE;
|
|
exception:
|
|
emulate_exception(ctxt, err_vec, err_code, true);
|
|
return X86EMUL_PROPAGATE_FAULT;
|
|
}
|
|
|
|
static void write_register_operand(struct operand *op)
|
|
{
|
|
/* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
|
|
switch (op->bytes) {
|
|
case 1:
|
|
*(u8 *)op->addr.reg = (u8)op->val;
|
|
break;
|
|
case 2:
|
|
*(u16 *)op->addr.reg = (u16)op->val;
|
|
break;
|
|
case 4:
|
|
*op->addr.reg = (u32)op->val;
|
|
break; /* 64b: zero-extend */
|
|
case 8:
|
|
*op->addr.reg = op->val;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
|
|
{
|
|
int rc;
|
|
|
|
switch (op->type) {
|
|
case OP_REG:
|
|
write_register_operand(op);
|
|
break;
|
|
case OP_MEM:
|
|
if (ctxt->lock_prefix)
|
|
rc = segmented_cmpxchg(ctxt,
|
|
op->addr.mem,
|
|
&op->orig_val,
|
|
&op->val,
|
|
op->bytes);
|
|
else
|
|
rc = segmented_write(ctxt,
|
|
op->addr.mem,
|
|
&op->val,
|
|
op->bytes);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
break;
|
|
case OP_MEM_STR:
|
|
rc = segmented_write(ctxt,
|
|
op->addr.mem,
|
|
op->data,
|
|
op->bytes * op->count);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
break;
|
|
case OP_XMM:
|
|
write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
|
|
break;
|
|
case OP_MM:
|
|
write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
|
|
break;
|
|
case OP_NONE:
|
|
/* no writeback */
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
|
|
{
|
|
struct segmented_address addr;
|
|
|
|
rsp_increment(ctxt, -bytes);
|
|
addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
|
|
addr.seg = VCPU_SREG_SS;
|
|
|
|
return segmented_write(ctxt, addr, data, bytes);
|
|
}
|
|
|
|
static int em_push(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
/* Disable writeback. */
|
|
ctxt->dst.type = OP_NONE;
|
|
return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
|
|
}
|
|
|
|
static int emulate_pop(struct x86_emulate_ctxt *ctxt,
|
|
void *dest, int len)
|
|
{
|
|
int rc;
|
|
struct segmented_address addr;
|
|
|
|
addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
|
|
addr.seg = VCPU_SREG_SS;
|
|
rc = segmented_read(ctxt, addr, dest, len);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
|
|
rsp_increment(ctxt, len);
|
|
return rc;
|
|
}
|
|
|
|
static int em_pop(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
|
|
}
|
|
|
|
static int emulate_popf(struct x86_emulate_ctxt *ctxt,
|
|
void *dest, int len)
|
|
{
|
|
int rc;
|
|
unsigned long val, change_mask;
|
|
int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
|
|
int cpl = ctxt->ops->cpl(ctxt);
|
|
|
|
rc = emulate_pop(ctxt, &val, len);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
|
|
change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
|
|
| EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
|
|
|
|
switch(ctxt->mode) {
|
|
case X86EMUL_MODE_PROT64:
|
|
case X86EMUL_MODE_PROT32:
|
|
case X86EMUL_MODE_PROT16:
|
|
if (cpl == 0)
|
|
change_mask |= EFLG_IOPL;
|
|
if (cpl <= iopl)
|
|
change_mask |= EFLG_IF;
|
|
break;
|
|
case X86EMUL_MODE_VM86:
|
|
if (iopl < 3)
|
|
return emulate_gp(ctxt, 0);
|
|
change_mask |= EFLG_IF;
|
|
break;
|
|
default: /* real mode */
|
|
change_mask |= (EFLG_IOPL | EFLG_IF);
|
|
break;
|
|
}
|
|
|
|
*(unsigned long *)dest =
|
|
(ctxt->eflags & ~change_mask) | (val & change_mask);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int em_popf(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
ctxt->dst.type = OP_REG;
|
|
ctxt->dst.addr.reg = &ctxt->eflags;
|
|
ctxt->dst.bytes = ctxt->op_bytes;
|
|
return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
|
|
}
|
|
|
|
static int em_enter(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
int rc;
|
|
unsigned frame_size = ctxt->src.val;
|
|
unsigned nesting_level = ctxt->src2.val & 31;
|
|
ulong rbp;
|
|
|
|
if (nesting_level)
|
|
return X86EMUL_UNHANDLEABLE;
|
|
|
|
rbp = reg_read(ctxt, VCPU_REGS_RBP);
|
|
rc = push(ctxt, &rbp, stack_size(ctxt));
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
|
|
stack_mask(ctxt));
|
|
assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
|
|
reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
|
|
stack_mask(ctxt));
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_leave(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
|
|
stack_mask(ctxt));
|
|
return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
|
|
}
|
|
|
|
static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
int seg = ctxt->src2.val;
|
|
|
|
ctxt->src.val = get_segment_selector(ctxt, seg);
|
|
|
|
return em_push(ctxt);
|
|
}
|
|
|
|
static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
int seg = ctxt->src2.val;
|
|
unsigned long selector;
|
|
int rc;
|
|
|
|
rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
|
|
rc = load_segment_descriptor(ctxt, (u16)selector, seg);
|
|
return rc;
|
|
}
|
|
|
|
static int em_pusha(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
|
|
int rc = X86EMUL_CONTINUE;
|
|
int reg = VCPU_REGS_RAX;
|
|
|
|
while (reg <= VCPU_REGS_RDI) {
|
|
(reg == VCPU_REGS_RSP) ?
|
|
(ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
|
|
|
|
rc = em_push(ctxt);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
|
|
++reg;
|
|
}
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int em_pushf(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
ctxt->src.val = (unsigned long)ctxt->eflags;
|
|
return em_push(ctxt);
|
|
}
|
|
|
|
static int em_popa(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
int rc = X86EMUL_CONTINUE;
|
|
int reg = VCPU_REGS_RDI;
|
|
|
|
while (reg >= VCPU_REGS_RAX) {
|
|
if (reg == VCPU_REGS_RSP) {
|
|
rsp_increment(ctxt, ctxt->op_bytes);
|
|
--reg;
|
|
}
|
|
|
|
rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
break;
|
|
--reg;
|
|
}
|
|
return rc;
|
|
}
|
|
|
|
static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
|
|
{
|
|
const struct x86_emulate_ops *ops = ctxt->ops;
|
|
int rc;
|
|
struct desc_ptr dt;
|
|
gva_t cs_addr;
|
|
gva_t eip_addr;
|
|
u16 cs, eip;
|
|
|
|
/* TODO: Add limit checks */
|
|
ctxt->src.val = ctxt->eflags;
|
|
rc = em_push(ctxt);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
|
|
ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
|
|
|
|
ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
|
|
rc = em_push(ctxt);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
|
|
ctxt->src.val = ctxt->_eip;
|
|
rc = em_push(ctxt);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
|
|
ops->get_idt(ctxt, &dt);
|
|
|
|
eip_addr = dt.address + (irq << 2);
|
|
cs_addr = dt.address + (irq << 2) + 2;
|
|
|
|
rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
|
|
rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
|
|
rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
|
|
ctxt->_eip = eip;
|
|
|
|
return rc;
|
|
}
|
|
|
|
int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
|
|
{
|
|
int rc;
|
|
|
|
invalidate_registers(ctxt);
|
|
rc = __emulate_int_real(ctxt, irq);
|
|
if (rc == X86EMUL_CONTINUE)
|
|
writeback_registers(ctxt);
|
|
return rc;
|
|
}
|
|
|
|
static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
|
|
{
|
|
switch(ctxt->mode) {
|
|
case X86EMUL_MODE_REAL:
|
|
return __emulate_int_real(ctxt, irq);
|
|
case X86EMUL_MODE_VM86:
|
|
case X86EMUL_MODE_PROT16:
|
|
case X86EMUL_MODE_PROT32:
|
|
case X86EMUL_MODE_PROT64:
|
|
default:
|
|
/* Protected mode interrupts unimplemented yet */
|
|
return X86EMUL_UNHANDLEABLE;
|
|
}
|
|
}
|
|
|
|
static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
int rc = X86EMUL_CONTINUE;
|
|
unsigned long temp_eip = 0;
|
|
unsigned long temp_eflags = 0;
|
|
unsigned long cs = 0;
|
|
unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
|
|
EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
|
|
EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
|
|
unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
|
|
|
|
/* TODO: Add stack limit check */
|
|
|
|
rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
|
|
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
|
|
if (temp_eip & ~0xffff)
|
|
return emulate_gp(ctxt, 0);
|
|
|
|
rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
|
|
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
|
|
rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
|
|
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
|
|
rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
|
|
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
|
|
ctxt->_eip = temp_eip;
|
|
|
|
|
|
if (ctxt->op_bytes == 4)
|
|
ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
|
|
else if (ctxt->op_bytes == 2) {
|
|
ctxt->eflags &= ~0xffff;
|
|
ctxt->eflags |= temp_eflags;
|
|
}
|
|
|
|
ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
|
|
ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int em_iret(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
switch(ctxt->mode) {
|
|
case X86EMUL_MODE_REAL:
|
|
return emulate_iret_real(ctxt);
|
|
case X86EMUL_MODE_VM86:
|
|
case X86EMUL_MODE_PROT16:
|
|
case X86EMUL_MODE_PROT32:
|
|
case X86EMUL_MODE_PROT64:
|
|
default:
|
|
/* iret from protected mode unimplemented yet */
|
|
return X86EMUL_UNHANDLEABLE;
|
|
}
|
|
}
|
|
|
|
static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
int rc;
|
|
unsigned short sel;
|
|
|
|
memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
|
|
|
|
rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
|
|
ctxt->_eip = 0;
|
|
memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_grp45(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
int rc = X86EMUL_CONTINUE;
|
|
|
|
switch (ctxt->modrm_reg) {
|
|
case 2: /* call near abs */ {
|
|
long int old_eip;
|
|
old_eip = ctxt->_eip;
|
|
ctxt->_eip = ctxt->src.val;
|
|
ctxt->src.val = old_eip;
|
|
rc = em_push(ctxt);
|
|
break;
|
|
}
|
|
case 4: /* jmp abs */
|
|
ctxt->_eip = ctxt->src.val;
|
|
break;
|
|
case 5: /* jmp far */
|
|
rc = em_jmp_far(ctxt);
|
|
break;
|
|
case 6: /* push */
|
|
rc = em_push(ctxt);
|
|
break;
|
|
}
|
|
return rc;
|
|
}
|
|
|
|
static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u64 old = ctxt->dst.orig_val64;
|
|
|
|
if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
|
|
((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
|
|
*reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
|
|
*reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
|
|
ctxt->eflags &= ~EFLG_ZF;
|
|
} else {
|
|
ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
|
|
(u32) reg_read(ctxt, VCPU_REGS_RBX);
|
|
|
|
ctxt->eflags |= EFLG_ZF;
|
|
}
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_ret(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
ctxt->dst.type = OP_REG;
|
|
ctxt->dst.addr.reg = &ctxt->_eip;
|
|
ctxt->dst.bytes = ctxt->op_bytes;
|
|
return em_pop(ctxt);
|
|
}
|
|
|
|
static int em_ret_far(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
int rc;
|
|
unsigned long cs;
|
|
|
|
rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
if (ctxt->op_bytes == 4)
|
|
ctxt->_eip = (u32)ctxt->_eip;
|
|
rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
|
|
return rc;
|
|
}
|
|
|
|
static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
int rc;
|
|
|
|
rc = em_ret_far(ctxt);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
rsp_increment(ctxt, ctxt->src.val);
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
/* Save real source value, then compare EAX against destination. */
|
|
ctxt->src.orig_val = ctxt->src.val;
|
|
ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
|
|
fastop(ctxt, em_cmp);
|
|
|
|
if (ctxt->eflags & EFLG_ZF) {
|
|
/* Success: write back to memory. */
|
|
ctxt->dst.val = ctxt->src.orig_val;
|
|
} else {
|
|
/* Failure: write the value we saw to EAX. */
|
|
ctxt->dst.type = OP_REG;
|
|
ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
|
|
}
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_lseg(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
int seg = ctxt->src2.val;
|
|
unsigned short sel;
|
|
int rc;
|
|
|
|
memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
|
|
|
|
rc = load_segment_descriptor(ctxt, sel, seg);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
|
|
ctxt->dst.val = ctxt->src.val;
|
|
return rc;
|
|
}
|
|
|
|
static void
|
|
setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
|
|
struct desc_struct *cs, struct desc_struct *ss)
|
|
{
|
|
cs->l = 0; /* will be adjusted later */
|
|
set_desc_base(cs, 0); /* flat segment */
|
|
cs->g = 1; /* 4kb granularity */
|
|
set_desc_limit(cs, 0xfffff); /* 4GB limit */
|
|
cs->type = 0x0b; /* Read, Execute, Accessed */
|
|
cs->s = 1;
|
|
cs->dpl = 0; /* will be adjusted later */
|
|
cs->p = 1;
|
|
cs->d = 1;
|
|
cs->avl = 0;
|
|
|
|
set_desc_base(ss, 0); /* flat segment */
|
|
set_desc_limit(ss, 0xfffff); /* 4GB limit */
|
|
ss->g = 1; /* 4kb granularity */
|
|
ss->s = 1;
|
|
ss->type = 0x03; /* Read/Write, Accessed */
|
|
ss->d = 1; /* 32bit stack segment */
|
|
ss->dpl = 0;
|
|
ss->p = 1;
|
|
ss->l = 0;
|
|
ss->avl = 0;
|
|
}
|
|
|
|
static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u32 eax, ebx, ecx, edx;
|
|
|
|
eax = ecx = 0;
|
|
ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
|
|
return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
|
|
&& ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
|
|
&& edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
|
|
}
|
|
|
|
static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
const struct x86_emulate_ops *ops = ctxt->ops;
|
|
u32 eax, ebx, ecx, edx;
|
|
|
|
/*
|
|
* syscall should always be enabled in longmode - so only become
|
|
* vendor specific (cpuid) if other modes are active...
|
|
*/
|
|
if (ctxt->mode == X86EMUL_MODE_PROT64)
|
|
return true;
|
|
|
|
eax = 0x00000000;
|
|
ecx = 0x00000000;
|
|
ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
|
|
/*
|
|
* Intel ("GenuineIntel")
|
|
* remark: Intel CPUs only support "syscall" in 64bit
|
|
* longmode. Also an 64bit guest with a
|
|
* 32bit compat-app running will #UD !! While this
|
|
* behaviour can be fixed (by emulating) into AMD
|
|
* response - CPUs of AMD can't behave like Intel.
|
|
*/
|
|
if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
|
|
ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
|
|
edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
|
|
return false;
|
|
|
|
/* AMD ("AuthenticAMD") */
|
|
if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
|
|
ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
|
|
edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
|
|
return true;
|
|
|
|
/* AMD ("AMDisbetter!") */
|
|
if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
|
|
ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
|
|
edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
|
|
return true;
|
|
|
|
/* default: (not Intel, not AMD), apply Intel's stricter rules... */
|
|
return false;
|
|
}
|
|
|
|
static int em_syscall(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
const struct x86_emulate_ops *ops = ctxt->ops;
|
|
struct desc_struct cs, ss;
|
|
u64 msr_data;
|
|
u16 cs_sel, ss_sel;
|
|
u64 efer = 0;
|
|
|
|
/* syscall is not available in real mode */
|
|
if (ctxt->mode == X86EMUL_MODE_REAL ||
|
|
ctxt->mode == X86EMUL_MODE_VM86)
|
|
return emulate_ud(ctxt);
|
|
|
|
if (!(em_syscall_is_enabled(ctxt)))
|
|
return emulate_ud(ctxt);
|
|
|
|
ops->get_msr(ctxt, MSR_EFER, &efer);
|
|
setup_syscalls_segments(ctxt, &cs, &ss);
|
|
|
|
if (!(efer & EFER_SCE))
|
|
return emulate_ud(ctxt);
|
|
|
|
ops->get_msr(ctxt, MSR_STAR, &msr_data);
|
|
msr_data >>= 32;
|
|
cs_sel = (u16)(msr_data & 0xfffc);
|
|
ss_sel = (u16)(msr_data + 8);
|
|
|
|
if (efer & EFER_LMA) {
|
|
cs.d = 0;
|
|
cs.l = 1;
|
|
}
|
|
ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
|
|
ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
|
|
|
|
*reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
|
|
if (efer & EFER_LMA) {
|
|
#ifdef CONFIG_X86_64
|
|
*reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
|
|
|
|
ops->get_msr(ctxt,
|
|
ctxt->mode == X86EMUL_MODE_PROT64 ?
|
|
MSR_LSTAR : MSR_CSTAR, &msr_data);
|
|
ctxt->_eip = msr_data;
|
|
|
|
ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
|
|
ctxt->eflags &= ~(msr_data | EFLG_RF);
|
|
#endif
|
|
} else {
|
|
/* legacy mode */
|
|
ops->get_msr(ctxt, MSR_STAR, &msr_data);
|
|
ctxt->_eip = (u32)msr_data;
|
|
|
|
ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
|
|
}
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_sysenter(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
const struct x86_emulate_ops *ops = ctxt->ops;
|
|
struct desc_struct cs, ss;
|
|
u64 msr_data;
|
|
u16 cs_sel, ss_sel;
|
|
u64 efer = 0;
|
|
|
|
ops->get_msr(ctxt, MSR_EFER, &efer);
|
|
/* inject #GP if in real mode */
|
|
if (ctxt->mode == X86EMUL_MODE_REAL)
|
|
return emulate_gp(ctxt, 0);
|
|
|
|
/*
|
|
* Not recognized on AMD in compat mode (but is recognized in legacy
|
|
* mode).
|
|
*/
|
|
if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
|
|
&& !vendor_intel(ctxt))
|
|
return emulate_ud(ctxt);
|
|
|
|
/* XXX sysenter/sysexit have not been tested in 64bit mode.
|
|
* Therefore, we inject an #UD.
|
|
*/
|
|
if (ctxt->mode == X86EMUL_MODE_PROT64)
|
|
return emulate_ud(ctxt);
|
|
|
|
setup_syscalls_segments(ctxt, &cs, &ss);
|
|
|
|
ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
|
|
switch (ctxt->mode) {
|
|
case X86EMUL_MODE_PROT32:
|
|
if ((msr_data & 0xfffc) == 0x0)
|
|
return emulate_gp(ctxt, 0);
|
|
break;
|
|
case X86EMUL_MODE_PROT64:
|
|
if (msr_data == 0x0)
|
|
return emulate_gp(ctxt, 0);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
|
|
cs_sel = (u16)msr_data;
|
|
cs_sel &= ~SELECTOR_RPL_MASK;
|
|
ss_sel = cs_sel + 8;
|
|
ss_sel &= ~SELECTOR_RPL_MASK;
|
|
if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
|
|
cs.d = 0;
|
|
cs.l = 1;
|
|
}
|
|
|
|
ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
|
|
ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
|
|
|
|
ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
|
|
ctxt->_eip = msr_data;
|
|
|
|
ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
|
|
*reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_sysexit(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
const struct x86_emulate_ops *ops = ctxt->ops;
|
|
struct desc_struct cs, ss;
|
|
u64 msr_data;
|
|
int usermode;
|
|
u16 cs_sel = 0, ss_sel = 0;
|
|
|
|
/* inject #GP if in real mode or Virtual 8086 mode */
|
|
if (ctxt->mode == X86EMUL_MODE_REAL ||
|
|
ctxt->mode == X86EMUL_MODE_VM86)
|
|
return emulate_gp(ctxt, 0);
|
|
|
|
setup_syscalls_segments(ctxt, &cs, &ss);
|
|
|
|
if ((ctxt->rex_prefix & 0x8) != 0x0)
|
|
usermode = X86EMUL_MODE_PROT64;
|
|
else
|
|
usermode = X86EMUL_MODE_PROT32;
|
|
|
|
cs.dpl = 3;
|
|
ss.dpl = 3;
|
|
ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
|
|
switch (usermode) {
|
|
case X86EMUL_MODE_PROT32:
|
|
cs_sel = (u16)(msr_data + 16);
|
|
if ((msr_data & 0xfffc) == 0x0)
|
|
return emulate_gp(ctxt, 0);
|
|
ss_sel = (u16)(msr_data + 24);
|
|
break;
|
|
case X86EMUL_MODE_PROT64:
|
|
cs_sel = (u16)(msr_data + 32);
|
|
if (msr_data == 0x0)
|
|
return emulate_gp(ctxt, 0);
|
|
ss_sel = cs_sel + 8;
|
|
cs.d = 0;
|
|
cs.l = 1;
|
|
break;
|
|
}
|
|
cs_sel |= SELECTOR_RPL_MASK;
|
|
ss_sel |= SELECTOR_RPL_MASK;
|
|
|
|
ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
|
|
ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
|
|
|
|
ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
|
|
*reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
int iopl;
|
|
if (ctxt->mode == X86EMUL_MODE_REAL)
|
|
return false;
|
|
if (ctxt->mode == X86EMUL_MODE_VM86)
|
|
return true;
|
|
iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
|
|
return ctxt->ops->cpl(ctxt) > iopl;
|
|
}
|
|
|
|
static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
|
|
u16 port, u16 len)
|
|
{
|
|
const struct x86_emulate_ops *ops = ctxt->ops;
|
|
struct desc_struct tr_seg;
|
|
u32 base3;
|
|
int r;
|
|
u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
|
|
unsigned mask = (1 << len) - 1;
|
|
unsigned long base;
|
|
|
|
ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
|
|
if (!tr_seg.p)
|
|
return false;
|
|
if (desc_limit_scaled(&tr_seg) < 103)
|
|
return false;
|
|
base = get_desc_base(&tr_seg);
|
|
#ifdef CONFIG_X86_64
|
|
base |= ((u64)base3) << 32;
|
|
#endif
|
|
r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
|
|
if (r != X86EMUL_CONTINUE)
|
|
return false;
|
|
if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
|
|
return false;
|
|
r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
|
|
if (r != X86EMUL_CONTINUE)
|
|
return false;
|
|
if ((perm >> bit_idx) & mask)
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
|
|
u16 port, u16 len)
|
|
{
|
|
if (ctxt->perm_ok)
|
|
return true;
|
|
|
|
if (emulator_bad_iopl(ctxt))
|
|
if (!emulator_io_port_access_allowed(ctxt, port, len))
|
|
return false;
|
|
|
|
ctxt->perm_ok = true;
|
|
|
|
return true;
|
|
}
|
|
|
|
static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
|
|
struct tss_segment_16 *tss)
|
|
{
|
|
tss->ip = ctxt->_eip;
|
|
tss->flag = ctxt->eflags;
|
|
tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
|
|
tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
|
|
tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
|
|
tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
|
|
tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
|
|
tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
|
|
tss->si = reg_read(ctxt, VCPU_REGS_RSI);
|
|
tss->di = reg_read(ctxt, VCPU_REGS_RDI);
|
|
|
|
tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
|
|
tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
|
|
tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
|
|
tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
|
|
tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
|
|
}
|
|
|
|
static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
|
|
struct tss_segment_16 *tss)
|
|
{
|
|
int ret;
|
|
|
|
ctxt->_eip = tss->ip;
|
|
ctxt->eflags = tss->flag | 2;
|
|
*reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
|
|
*reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
|
|
*reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
|
|
*reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
|
|
*reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
|
|
*reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
|
|
*reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
|
|
*reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
|
|
|
|
/*
|
|
* SDM says that segment selectors are loaded before segment
|
|
* descriptors
|
|
*/
|
|
set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
|
|
set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
|
|
set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
|
|
set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
|
|
set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
|
|
|
|
/*
|
|
* Now load segment descriptors. If fault happens at this stage
|
|
* it is handled in a context of new task
|
|
*/
|
|
ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
return ret;
|
|
ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
return ret;
|
|
ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
return ret;
|
|
ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
return ret;
|
|
ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
return ret;
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int task_switch_16(struct x86_emulate_ctxt *ctxt,
|
|
u16 tss_selector, u16 old_tss_sel,
|
|
ulong old_tss_base, struct desc_struct *new_desc)
|
|
{
|
|
const struct x86_emulate_ops *ops = ctxt->ops;
|
|
struct tss_segment_16 tss_seg;
|
|
int ret;
|
|
u32 new_tss_base = get_desc_base(new_desc);
|
|
|
|
ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
|
|
&ctxt->exception);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
/* FIXME: need to provide precise fault address */
|
|
return ret;
|
|
|
|
save_state_to_tss16(ctxt, &tss_seg);
|
|
|
|
ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
|
|
&ctxt->exception);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
/* FIXME: need to provide precise fault address */
|
|
return ret;
|
|
|
|
ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
|
|
&ctxt->exception);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
/* FIXME: need to provide precise fault address */
|
|
return ret;
|
|
|
|
if (old_tss_sel != 0xffff) {
|
|
tss_seg.prev_task_link = old_tss_sel;
|
|
|
|
ret = ops->write_std(ctxt, new_tss_base,
|
|
&tss_seg.prev_task_link,
|
|
sizeof tss_seg.prev_task_link,
|
|
&ctxt->exception);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
/* FIXME: need to provide precise fault address */
|
|
return ret;
|
|
}
|
|
|
|
return load_state_from_tss16(ctxt, &tss_seg);
|
|
}
|
|
|
|
static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
|
|
struct tss_segment_32 *tss)
|
|
{
|
|
tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
|
|
tss->eip = ctxt->_eip;
|
|
tss->eflags = ctxt->eflags;
|
|
tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
|
|
tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
|
|
tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
|
|
tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
|
|
tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
|
|
tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
|
|
tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
|
|
tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
|
|
|
|
tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
|
|
tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
|
|
tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
|
|
tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
|
|
tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
|
|
tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
|
|
tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
|
|
}
|
|
|
|
static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
|
|
struct tss_segment_32 *tss)
|
|
{
|
|
int ret;
|
|
|
|
if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
|
|
return emulate_gp(ctxt, 0);
|
|
ctxt->_eip = tss->eip;
|
|
ctxt->eflags = tss->eflags | 2;
|
|
|
|
/* General purpose registers */
|
|
*reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
|
|
*reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
|
|
*reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
|
|
*reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
|
|
*reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
|
|
*reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
|
|
*reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
|
|
*reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
|
|
|
|
/*
|
|
* SDM says that segment selectors are loaded before segment
|
|
* descriptors
|
|
*/
|
|
set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
|
|
set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
|
|
set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
|
|
set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
|
|
set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
|
|
set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
|
|
set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
|
|
|
|
/*
|
|
* If we're switching between Protected Mode and VM86, we need to make
|
|
* sure to update the mode before loading the segment descriptors so
|
|
* that the selectors are interpreted correctly.
|
|
*
|
|
* Need to get rflags to the vcpu struct immediately because it
|
|
* influences the CPL which is checked at least when loading the segment
|
|
* descriptors and when pushing an error code to the new kernel stack.
|
|
*
|
|
* TODO Introduce a separate ctxt->ops->set_cpl callback
|
|
*/
|
|
if (ctxt->eflags & X86_EFLAGS_VM)
|
|
ctxt->mode = X86EMUL_MODE_VM86;
|
|
else
|
|
ctxt->mode = X86EMUL_MODE_PROT32;
|
|
|
|
ctxt->ops->set_rflags(ctxt, ctxt->eflags);
|
|
|
|
/*
|
|
* Now load segment descriptors. If fault happenes at this stage
|
|
* it is handled in a context of new task
|
|
*/
|
|
ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
return ret;
|
|
ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
return ret;
|
|
ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
return ret;
|
|
ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
return ret;
|
|
ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
return ret;
|
|
ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
return ret;
|
|
ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
return ret;
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int task_switch_32(struct x86_emulate_ctxt *ctxt,
|
|
u16 tss_selector, u16 old_tss_sel,
|
|
ulong old_tss_base, struct desc_struct *new_desc)
|
|
{
|
|
const struct x86_emulate_ops *ops = ctxt->ops;
|
|
struct tss_segment_32 tss_seg;
|
|
int ret;
|
|
u32 new_tss_base = get_desc_base(new_desc);
|
|
|
|
ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
|
|
&ctxt->exception);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
/* FIXME: need to provide precise fault address */
|
|
return ret;
|
|
|
|
save_state_to_tss32(ctxt, &tss_seg);
|
|
|
|
ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
|
|
&ctxt->exception);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
/* FIXME: need to provide precise fault address */
|
|
return ret;
|
|
|
|
ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
|
|
&ctxt->exception);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
/* FIXME: need to provide precise fault address */
|
|
return ret;
|
|
|
|
if (old_tss_sel != 0xffff) {
|
|
tss_seg.prev_task_link = old_tss_sel;
|
|
|
|
ret = ops->write_std(ctxt, new_tss_base,
|
|
&tss_seg.prev_task_link,
|
|
sizeof tss_seg.prev_task_link,
|
|
&ctxt->exception);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
/* FIXME: need to provide precise fault address */
|
|
return ret;
|
|
}
|
|
|
|
return load_state_from_tss32(ctxt, &tss_seg);
|
|
}
|
|
|
|
static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
|
|
u16 tss_selector, int idt_index, int reason,
|
|
bool has_error_code, u32 error_code)
|
|
{
|
|
const struct x86_emulate_ops *ops = ctxt->ops;
|
|
struct desc_struct curr_tss_desc, next_tss_desc;
|
|
int ret;
|
|
u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
|
|
ulong old_tss_base =
|
|
ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
|
|
u32 desc_limit;
|
|
ulong desc_addr;
|
|
|
|
/* FIXME: old_tss_base == ~0 ? */
|
|
|
|
ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
return ret;
|
|
ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
return ret;
|
|
|
|
/* FIXME: check that next_tss_desc is tss */
|
|
|
|
/*
|
|
* Check privileges. The three cases are task switch caused by...
|
|
*
|
|
* 1. jmp/call/int to task gate: Check against DPL of the task gate
|
|
* 2. Exception/IRQ/iret: No check is performed
|
|
* 3. jmp/call to TSS: Check against DPL of the TSS
|
|
*/
|
|
if (reason == TASK_SWITCH_GATE) {
|
|
if (idt_index != -1) {
|
|
/* Software interrupts */
|
|
struct desc_struct task_gate_desc;
|
|
int dpl;
|
|
|
|
ret = read_interrupt_descriptor(ctxt, idt_index,
|
|
&task_gate_desc);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
return ret;
|
|
|
|
dpl = task_gate_desc.dpl;
|
|
if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
|
|
return emulate_gp(ctxt, (idt_index << 3) | 0x2);
|
|
}
|
|
} else if (reason != TASK_SWITCH_IRET) {
|
|
int dpl = next_tss_desc.dpl;
|
|
if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
|
|
return emulate_gp(ctxt, tss_selector);
|
|
}
|
|
|
|
|
|
desc_limit = desc_limit_scaled(&next_tss_desc);
|
|
if (!next_tss_desc.p ||
|
|
((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
|
|
desc_limit < 0x2b)) {
|
|
emulate_ts(ctxt, tss_selector & 0xfffc);
|
|
return X86EMUL_PROPAGATE_FAULT;
|
|
}
|
|
|
|
if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
|
|
curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
|
|
write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
|
|
}
|
|
|
|
if (reason == TASK_SWITCH_IRET)
|
|
ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
|
|
|
|
/* set back link to prev task only if NT bit is set in eflags
|
|
note that old_tss_sel is not used after this point */
|
|
if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
|
|
old_tss_sel = 0xffff;
|
|
|
|
if (next_tss_desc.type & 8)
|
|
ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
|
|
old_tss_base, &next_tss_desc);
|
|
else
|
|
ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
|
|
old_tss_base, &next_tss_desc);
|
|
if (ret != X86EMUL_CONTINUE)
|
|
return ret;
|
|
|
|
if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
|
|
ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
|
|
|
|
if (reason != TASK_SWITCH_IRET) {
|
|
next_tss_desc.type |= (1 << 1); /* set busy flag */
|
|
write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
|
|
}
|
|
|
|
ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
|
|
ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
|
|
|
|
if (has_error_code) {
|
|
ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
|
|
ctxt->lock_prefix = 0;
|
|
ctxt->src.val = (unsigned long) error_code;
|
|
ret = em_push(ctxt);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
|
|
u16 tss_selector, int idt_index, int reason,
|
|
bool has_error_code, u32 error_code)
|
|
{
|
|
int rc;
|
|
|
|
invalidate_registers(ctxt);
|
|
ctxt->_eip = ctxt->eip;
|
|
ctxt->dst.type = OP_NONE;
|
|
|
|
rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
|
|
has_error_code, error_code);
|
|
|
|
if (rc == X86EMUL_CONTINUE) {
|
|
ctxt->eip = ctxt->_eip;
|
|
writeback_registers(ctxt);
|
|
}
|
|
|
|
return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
|
|
}
|
|
|
|
static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
|
|
struct operand *op)
|
|
{
|
|
int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
|
|
|
|
register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
|
|
op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
|
|
}
|
|
|
|
static int em_das(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u8 al, old_al;
|
|
bool af, cf, old_cf;
|
|
|
|
cf = ctxt->eflags & X86_EFLAGS_CF;
|
|
al = ctxt->dst.val;
|
|
|
|
old_al = al;
|
|
old_cf = cf;
|
|
cf = false;
|
|
af = ctxt->eflags & X86_EFLAGS_AF;
|
|
if ((al & 0x0f) > 9 || af) {
|
|
al -= 6;
|
|
cf = old_cf | (al >= 250);
|
|
af = true;
|
|
} else {
|
|
af = false;
|
|
}
|
|
if (old_al > 0x99 || old_cf) {
|
|
al -= 0x60;
|
|
cf = true;
|
|
}
|
|
|
|
ctxt->dst.val = al;
|
|
/* Set PF, ZF, SF */
|
|
ctxt->src.type = OP_IMM;
|
|
ctxt->src.val = 0;
|
|
ctxt->src.bytes = 1;
|
|
fastop(ctxt, em_or);
|
|
ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
|
|
if (cf)
|
|
ctxt->eflags |= X86_EFLAGS_CF;
|
|
if (af)
|
|
ctxt->eflags |= X86_EFLAGS_AF;
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_aam(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u8 al, ah;
|
|
|
|
if (ctxt->src.val == 0)
|
|
return emulate_de(ctxt);
|
|
|
|
al = ctxt->dst.val & 0xff;
|
|
ah = al / ctxt->src.val;
|
|
al %= ctxt->src.val;
|
|
|
|
ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
|
|
|
|
/* Set PF, ZF, SF */
|
|
ctxt->src.type = OP_IMM;
|
|
ctxt->src.val = 0;
|
|
ctxt->src.bytes = 1;
|
|
fastop(ctxt, em_or);
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_aad(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u8 al = ctxt->dst.val & 0xff;
|
|
u8 ah = (ctxt->dst.val >> 8) & 0xff;
|
|
|
|
al = (al + (ah * ctxt->src.val)) & 0xff;
|
|
|
|
ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
|
|
|
|
/* Set PF, ZF, SF */
|
|
ctxt->src.type = OP_IMM;
|
|
ctxt->src.val = 0;
|
|
ctxt->src.bytes = 1;
|
|
fastop(ctxt, em_or);
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_call(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
long rel = ctxt->src.val;
|
|
|
|
ctxt->src.val = (unsigned long)ctxt->_eip;
|
|
jmp_rel(ctxt, rel);
|
|
return em_push(ctxt);
|
|
}
|
|
|
|
static int em_call_far(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u16 sel, old_cs;
|
|
ulong old_eip;
|
|
int rc;
|
|
|
|
old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
|
|
old_eip = ctxt->_eip;
|
|
|
|
memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
|
|
if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
|
|
return X86EMUL_CONTINUE;
|
|
|
|
ctxt->_eip = 0;
|
|
memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
|
|
|
|
ctxt->src.val = old_cs;
|
|
rc = em_push(ctxt);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
|
|
ctxt->src.val = old_eip;
|
|
return em_push(ctxt);
|
|
}
|
|
|
|
static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
int rc;
|
|
|
|
ctxt->dst.type = OP_REG;
|
|
ctxt->dst.addr.reg = &ctxt->_eip;
|
|
ctxt->dst.bytes = ctxt->op_bytes;
|
|
rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
rsp_increment(ctxt, ctxt->src.val);
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_xchg(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
/* Write back the register source. */
|
|
ctxt->src.val = ctxt->dst.val;
|
|
write_register_operand(&ctxt->src);
|
|
|
|
/* Write back the memory destination with implicit LOCK prefix. */
|
|
ctxt->dst.val = ctxt->src.orig_val;
|
|
ctxt->lock_prefix = 1;
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
ctxt->dst.val = ctxt->src2.val;
|
|
return fastop(ctxt, em_imul);
|
|
}
|
|
|
|
static int em_cwd(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
ctxt->dst.type = OP_REG;
|
|
ctxt->dst.bytes = ctxt->src.bytes;
|
|
ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
|
|
ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u64 tsc = 0;
|
|
|
|
ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
|
|
*reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
|
|
*reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u64 pmc;
|
|
|
|
if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
|
|
return emulate_gp(ctxt, 0);
|
|
*reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
|
|
*reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_mov(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
#define FFL(x) bit(X86_FEATURE_##x)
|
|
|
|
static int em_movbe(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u32 ebx, ecx, edx, eax = 1;
|
|
u16 tmp;
|
|
|
|
/*
|
|
* Check MOVBE is set in the guest-visible CPUID leaf.
|
|
*/
|
|
ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
|
|
if (!(ecx & FFL(MOVBE)))
|
|
return emulate_ud(ctxt);
|
|
|
|
switch (ctxt->op_bytes) {
|
|
case 2:
|
|
/*
|
|
* From MOVBE definition: "...When the operand size is 16 bits,
|
|
* the upper word of the destination register remains unchanged
|
|
* ..."
|
|
*
|
|
* Both casting ->valptr and ->val to u16 breaks strict aliasing
|
|
* rules so we have to do the operation almost per hand.
|
|
*/
|
|
tmp = (u16)ctxt->src.val;
|
|
ctxt->dst.val &= ~0xffffUL;
|
|
ctxt->dst.val |= (unsigned long)swab16(tmp);
|
|
break;
|
|
case 4:
|
|
ctxt->dst.val = swab32((u32)ctxt->src.val);
|
|
break;
|
|
case 8:
|
|
ctxt->dst.val = swab64(ctxt->src.val);
|
|
break;
|
|
default:
|
|
return X86EMUL_PROPAGATE_FAULT;
|
|
}
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_cr_write(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
|
|
return emulate_gp(ctxt, 0);
|
|
|
|
/* Disable writeback. */
|
|
ctxt->dst.type = OP_NONE;
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_dr_write(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
unsigned long val;
|
|
|
|
if (ctxt->mode == X86EMUL_MODE_PROT64)
|
|
val = ctxt->src.val & ~0ULL;
|
|
else
|
|
val = ctxt->src.val & ~0U;
|
|
|
|
/* #UD condition is already handled. */
|
|
if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
|
|
return emulate_gp(ctxt, 0);
|
|
|
|
/* Disable writeback. */
|
|
ctxt->dst.type = OP_NONE;
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u64 msr_data;
|
|
|
|
msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
|
|
| ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
|
|
if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
|
|
return emulate_gp(ctxt, 0);
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u64 msr_data;
|
|
|
|
if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
|
|
return emulate_gp(ctxt, 0);
|
|
|
|
*reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
|
|
*reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
if (ctxt->modrm_reg > VCPU_SREG_GS)
|
|
return emulate_ud(ctxt);
|
|
|
|
ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u16 sel = ctxt->src.val;
|
|
|
|
if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
|
|
return emulate_ud(ctxt);
|
|
|
|
if (ctxt->modrm_reg == VCPU_SREG_SS)
|
|
ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
|
|
|
|
/* Disable writeback. */
|
|
ctxt->dst.type = OP_NONE;
|
|
return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
|
|
}
|
|
|
|
static int em_lldt(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u16 sel = ctxt->src.val;
|
|
|
|
/* Disable writeback. */
|
|
ctxt->dst.type = OP_NONE;
|
|
return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
|
|
}
|
|
|
|
static int em_ltr(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u16 sel = ctxt->src.val;
|
|
|
|
/* Disable writeback. */
|
|
ctxt->dst.type = OP_NONE;
|
|
return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
|
|
}
|
|
|
|
static int em_invlpg(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
int rc;
|
|
ulong linear;
|
|
|
|
rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
|
|
if (rc == X86EMUL_CONTINUE)
|
|
ctxt->ops->invlpg(ctxt, linear);
|
|
/* Disable writeback. */
|
|
ctxt->dst.type = OP_NONE;
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_clts(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
ulong cr0;
|
|
|
|
cr0 = ctxt->ops->get_cr(ctxt, 0);
|
|
cr0 &= ~X86_CR0_TS;
|
|
ctxt->ops->set_cr(ctxt, 0, cr0);
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_vmcall(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
int rc;
|
|
|
|
if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
|
|
return X86EMUL_UNHANDLEABLE;
|
|
|
|
rc = ctxt->ops->fix_hypercall(ctxt);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
|
|
/* Let the processor re-execute the fixed hypercall */
|
|
ctxt->_eip = ctxt->eip;
|
|
/* Disable writeback. */
|
|
ctxt->dst.type = OP_NONE;
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
|
|
void (*get)(struct x86_emulate_ctxt *ctxt,
|
|
struct desc_ptr *ptr))
|
|
{
|
|
struct desc_ptr desc_ptr;
|
|
|
|
if (ctxt->mode == X86EMUL_MODE_PROT64)
|
|
ctxt->op_bytes = 8;
|
|
get(ctxt, &desc_ptr);
|
|
if (ctxt->op_bytes == 2) {
|
|
ctxt->op_bytes = 4;
|
|
desc_ptr.address &= 0x00ffffff;
|
|
}
|
|
/* Disable writeback. */
|
|
ctxt->dst.type = OP_NONE;
|
|
return segmented_write(ctxt, ctxt->dst.addr.mem,
|
|
&desc_ptr, 2 + ctxt->op_bytes);
|
|
}
|
|
|
|
static int em_sgdt(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
|
|
}
|
|
|
|
static int em_sidt(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
|
|
}
|
|
|
|
static int em_lgdt(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
struct desc_ptr desc_ptr;
|
|
int rc;
|
|
|
|
if (ctxt->mode == X86EMUL_MODE_PROT64)
|
|
ctxt->op_bytes = 8;
|
|
rc = read_descriptor(ctxt, ctxt->src.addr.mem,
|
|
&desc_ptr.size, &desc_ptr.address,
|
|
ctxt->op_bytes);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
ctxt->ops->set_gdt(ctxt, &desc_ptr);
|
|
/* Disable writeback. */
|
|
ctxt->dst.type = OP_NONE;
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
int rc;
|
|
|
|
rc = ctxt->ops->fix_hypercall(ctxt);
|
|
|
|
/* Disable writeback. */
|
|
ctxt->dst.type = OP_NONE;
|
|
return rc;
|
|
}
|
|
|
|
static int em_lidt(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
struct desc_ptr desc_ptr;
|
|
int rc;
|
|
|
|
if (ctxt->mode == X86EMUL_MODE_PROT64)
|
|
ctxt->op_bytes = 8;
|
|
rc = read_descriptor(ctxt, ctxt->src.addr.mem,
|
|
&desc_ptr.size, &desc_ptr.address,
|
|
ctxt->op_bytes);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
return rc;
|
|
ctxt->ops->set_idt(ctxt, &desc_ptr);
|
|
/* Disable writeback. */
|
|
ctxt->dst.type = OP_NONE;
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_smsw(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
ctxt->dst.bytes = 2;
|
|
ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_lmsw(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
|
|
| (ctxt->src.val & 0x0f));
|
|
ctxt->dst.type = OP_NONE;
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_loop(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
|
|
if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
|
|
(ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
|
|
jmp_rel(ctxt, ctxt->src.val);
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_jcxz(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
|
|
jmp_rel(ctxt, ctxt->src.val);
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_in(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
|
|
&ctxt->dst.val))
|
|
return X86EMUL_IO_NEEDED;
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_out(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
|
|
&ctxt->src.val, 1);
|
|
/* Disable writeback. */
|
|
ctxt->dst.type = OP_NONE;
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_cli(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
if (emulator_bad_iopl(ctxt))
|
|
return emulate_gp(ctxt, 0);
|
|
|
|
ctxt->eflags &= ~X86_EFLAGS_IF;
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_sti(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
if (emulator_bad_iopl(ctxt))
|
|
return emulate_gp(ctxt, 0);
|
|
|
|
ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
|
|
ctxt->eflags |= X86_EFLAGS_IF;
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_cpuid(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u32 eax, ebx, ecx, edx;
|
|
|
|
eax = reg_read(ctxt, VCPU_REGS_RAX);
|
|
ecx = reg_read(ctxt, VCPU_REGS_RCX);
|
|
ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
|
|
*reg_write(ctxt, VCPU_REGS_RAX) = eax;
|
|
*reg_write(ctxt, VCPU_REGS_RBX) = ebx;
|
|
*reg_write(ctxt, VCPU_REGS_RCX) = ecx;
|
|
*reg_write(ctxt, VCPU_REGS_RDX) = edx;
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_sahf(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u32 flags;
|
|
|
|
flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
|
|
flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
|
|
|
|
ctxt->eflags &= ~0xffUL;
|
|
ctxt->eflags |= flags | X86_EFLAGS_FIXED;
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_lahf(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
*reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
|
|
*reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int em_bswap(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
switch (ctxt->op_bytes) {
|
|
#ifdef CONFIG_X86_64
|
|
case 8:
|
|
asm("bswap %0" : "+r"(ctxt->dst.val));
|
|
break;
|
|
#endif
|
|
default:
|
|
asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
|
|
break;
|
|
}
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static bool valid_cr(int nr)
|
|
{
|
|
switch (nr) {
|
|
case 0:
|
|
case 2 ... 4:
|
|
case 8:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static int check_cr_read(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
if (!valid_cr(ctxt->modrm_reg))
|
|
return emulate_ud(ctxt);
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int check_cr_write(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u64 new_val = ctxt->src.val64;
|
|
int cr = ctxt->modrm_reg;
|
|
u64 efer = 0;
|
|
|
|
static u64 cr_reserved_bits[] = {
|
|
0xffffffff00000000ULL,
|
|
0, 0, 0, /* CR3 checked later */
|
|
CR4_RESERVED_BITS,
|
|
0, 0, 0,
|
|
CR8_RESERVED_BITS,
|
|
};
|
|
|
|
if (!valid_cr(cr))
|
|
return emulate_ud(ctxt);
|
|
|
|
if (new_val & cr_reserved_bits[cr])
|
|
return emulate_gp(ctxt, 0);
|
|
|
|
switch (cr) {
|
|
case 0: {
|
|
u64 cr4;
|
|
if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
|
|
((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
|
|
return emulate_gp(ctxt, 0);
|
|
|
|
cr4 = ctxt->ops->get_cr(ctxt, 4);
|
|
ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
|
|
|
|
if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
|
|
!(cr4 & X86_CR4_PAE))
|
|
return emulate_gp(ctxt, 0);
|
|
|
|
break;
|
|
}
|
|
case 3: {
|
|
u64 rsvd = 0;
|
|
|
|
ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
|
|
if (efer & EFER_LMA)
|
|
rsvd = CR3_L_MODE_RESERVED_BITS;
|
|
else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
|
|
rsvd = CR3_PAE_RESERVED_BITS;
|
|
else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
|
|
rsvd = CR3_NONPAE_RESERVED_BITS;
|
|
|
|
if (new_val & rsvd)
|
|
return emulate_gp(ctxt, 0);
|
|
|
|
break;
|
|
}
|
|
case 4: {
|
|
ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
|
|
|
|
if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
|
|
return emulate_gp(ctxt, 0);
|
|
|
|
break;
|
|
}
|
|
}
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
unsigned long dr7;
|
|
|
|
ctxt->ops->get_dr(ctxt, 7, &dr7);
|
|
|
|
/* Check if DR7.Global_Enable is set */
|
|
return dr7 & (1 << 13);
|
|
}
|
|
|
|
static int check_dr_read(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
int dr = ctxt->modrm_reg;
|
|
u64 cr4;
|
|
|
|
if (dr > 7)
|
|
return emulate_ud(ctxt);
|
|
|
|
cr4 = ctxt->ops->get_cr(ctxt, 4);
|
|
if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
|
|
return emulate_ud(ctxt);
|
|
|
|
if (check_dr7_gd(ctxt))
|
|
return emulate_db(ctxt);
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int check_dr_write(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u64 new_val = ctxt->src.val64;
|
|
int dr = ctxt->modrm_reg;
|
|
|
|
if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
|
|
return emulate_gp(ctxt, 0);
|
|
|
|
return check_dr_read(ctxt);
|
|
}
|
|
|
|
static int check_svme(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u64 efer;
|
|
|
|
ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
|
|
|
|
if (!(efer & EFER_SVME))
|
|
return emulate_ud(ctxt);
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
|
|
|
|
/* Valid physical address? */
|
|
if (rax & 0xffff000000000000ULL)
|
|
return emulate_gp(ctxt, 0);
|
|
|
|
return check_svme(ctxt);
|
|
}
|
|
|
|
static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
|
|
|
|
if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
|
|
return emulate_ud(ctxt);
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
|
|
u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
|
|
|
|
if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
|
|
(rcx > 3))
|
|
return emulate_gp(ctxt, 0);
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int check_perm_in(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
|
|
if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
|
|
return emulate_gp(ctxt, 0);
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static int check_perm_out(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
ctxt->src.bytes = min(ctxt->src.bytes, 4u);
|
|
if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
|
|
return emulate_gp(ctxt, 0);
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
#define D(_y) { .flags = (_y) }
|
|
#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
|
|
#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
|
|
.check_perm = (_p) }
|
|
#define N D(NotImpl)
|
|
#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
|
|
#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
|
|
#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
|
|
#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
|
|
#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
|
|
#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
|
|
#define II(_f, _e, _i) \
|
|
{ .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
|
|
#define IIP(_f, _e, _i, _p) \
|
|
{ .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
|
|
.check_perm = (_p) }
|
|
#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
|
|
|
|
#define D2bv(_f) D((_f) | ByteOp), D(_f)
|
|
#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
|
|
#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
|
|
#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
|
|
#define I2bvIP(_f, _e, _i, _p) \
|
|
IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
|
|
|
|
#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
|
|
F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
|
|
F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
|
|
|
|
static const struct opcode group7_rm1[] = {
|
|
DI(SrcNone | Priv, monitor),
|
|
DI(SrcNone | Priv, mwait),
|
|
N, N, N, N, N, N,
|
|
};
|
|
|
|
static const struct opcode group7_rm3[] = {
|
|
DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
|
|
II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
|
|
DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
|
|
DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
|
|
DIP(SrcNone | Prot | Priv, stgi, check_svme),
|
|
DIP(SrcNone | Prot | Priv, clgi, check_svme),
|
|
DIP(SrcNone | Prot | Priv, skinit, check_svme),
|
|
DIP(SrcNone | Prot | Priv, invlpga, check_svme),
|
|
};
|
|
|
|
static const struct opcode group7_rm7[] = {
|
|
N,
|
|
DIP(SrcNone, rdtscp, check_rdtsc),
|
|
N, N, N, N, N, N,
|
|
};
|
|
|
|
static const struct opcode group1[] = {
|
|
F(Lock, em_add),
|
|
F(Lock | PageTable, em_or),
|
|
F(Lock, em_adc),
|
|
F(Lock, em_sbb),
|
|
F(Lock | PageTable, em_and),
|
|
F(Lock, em_sub),
|
|
F(Lock, em_xor),
|
|
F(NoWrite, em_cmp),
|
|
};
|
|
|
|
static const struct opcode group1A[] = {
|
|
I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
|
|
};
|
|
|
|
static const struct opcode group2[] = {
|
|
F(DstMem | ModRM, em_rol),
|
|
F(DstMem | ModRM, em_ror),
|
|
F(DstMem | ModRM, em_rcl),
|
|
F(DstMem | ModRM, em_rcr),
|
|
F(DstMem | ModRM, em_shl),
|
|
F(DstMem | ModRM, em_shr),
|
|
F(DstMem | ModRM, em_shl),
|
|
F(DstMem | ModRM, em_sar),
|
|
};
|
|
|
|
static const struct opcode group3[] = {
|
|
F(DstMem | SrcImm | NoWrite, em_test),
|
|
F(DstMem | SrcImm | NoWrite, em_test),
|
|
F(DstMem | SrcNone | Lock, em_not),
|
|
F(DstMem | SrcNone | Lock, em_neg),
|
|
F(DstXacc | Src2Mem, em_mul_ex),
|
|
F(DstXacc | Src2Mem, em_imul_ex),
|
|
F(DstXacc | Src2Mem, em_div_ex),
|
|
F(DstXacc | Src2Mem, em_idiv_ex),
|
|
};
|
|
|
|
static const struct opcode group4[] = {
|
|
F(ByteOp | DstMem | SrcNone | Lock, em_inc),
|
|
F(ByteOp | DstMem | SrcNone | Lock, em_dec),
|
|
N, N, N, N, N, N,
|
|
};
|
|
|
|
static const struct opcode group5[] = {
|
|
F(DstMem | SrcNone | Lock, em_inc),
|
|
F(DstMem | SrcNone | Lock, em_dec),
|
|
I(SrcMem | Stack, em_grp45),
|
|
I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
|
|
I(SrcMem | Stack, em_grp45),
|
|
I(SrcMemFAddr | ImplicitOps, em_grp45),
|
|
I(SrcMem | Stack, em_grp45), D(Undefined),
|
|
};
|
|
|
|
static const struct opcode group6[] = {
|
|
DI(Prot, sldt),
|
|
DI(Prot, str),
|
|
II(Prot | Priv | SrcMem16, em_lldt, lldt),
|
|
II(Prot | Priv | SrcMem16, em_ltr, ltr),
|
|
N, N, N, N,
|
|
};
|
|
|
|
static const struct group_dual group7 = { {
|
|
II(Mov | DstMem | Priv, em_sgdt, sgdt),
|
|
II(Mov | DstMem | Priv, em_sidt, sidt),
|
|
II(SrcMem | Priv, em_lgdt, lgdt),
|
|
II(SrcMem | Priv, em_lidt, lidt),
|
|
II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
|
|
II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
|
|
II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
|
|
}, {
|
|
I(SrcNone | Priv | EmulateOnUD, em_vmcall),
|
|
EXT(0, group7_rm1),
|
|
N, EXT(0, group7_rm3),
|
|
II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
|
|
II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
|
|
EXT(0, group7_rm7),
|
|
} };
|
|
|
|
static const struct opcode group8[] = {
|
|
N, N, N, N,
|
|
F(DstMem | SrcImmByte | NoWrite, em_bt),
|
|
F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
|
|
F(DstMem | SrcImmByte | Lock, em_btr),
|
|
F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
|
|
};
|
|
|
|
static const struct group_dual group9 = { {
|
|
N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
|
|
}, {
|
|
N, N, N, N, N, N, N, N,
|
|
} };
|
|
|
|
static const struct opcode group11[] = {
|
|
I(DstMem | SrcImm | Mov | PageTable, em_mov),
|
|
X7(D(Undefined)),
|
|
};
|
|
|
|
static const struct gprefix pfx_0f_6f_0f_7f = {
|
|
I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
|
|
};
|
|
|
|
static const struct gprefix pfx_vmovntpx = {
|
|
I(0, em_mov), N, N, N,
|
|
};
|
|
|
|
static const struct gprefix pfx_0f_28_0f_29 = {
|
|
I(Aligned, em_mov), I(Aligned, em_mov), N, N,
|
|
};
|
|
|
|
static const struct escape escape_d9 = { {
|
|
N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
|
|
}, {
|
|
/* 0xC0 - 0xC7 */
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0xC8 - 0xCF */
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0xD0 - 0xC7 */
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0xD8 - 0xDF */
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0xE0 - 0xE7 */
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0xE8 - 0xEF */
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0xF0 - 0xF7 */
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0xF8 - 0xFF */
|
|
N, N, N, N, N, N, N, N,
|
|
} };
|
|
|
|
static const struct escape escape_db = { {
|
|
N, N, N, N, N, N, N, N,
|
|
}, {
|
|
/* 0xC0 - 0xC7 */
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0xC8 - 0xCF */
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0xD0 - 0xC7 */
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0xD8 - 0xDF */
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0xE0 - 0xE7 */
|
|
N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
|
|
/* 0xE8 - 0xEF */
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0xF0 - 0xF7 */
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0xF8 - 0xFF */
|
|
N, N, N, N, N, N, N, N,
|
|
} };
|
|
|
|
static const struct escape escape_dd = { {
|
|
N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
|
|
}, {
|
|
/* 0xC0 - 0xC7 */
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0xC8 - 0xCF */
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0xD0 - 0xC7 */
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0xD8 - 0xDF */
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0xE0 - 0xE7 */
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0xE8 - 0xEF */
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0xF0 - 0xF7 */
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0xF8 - 0xFF */
|
|
N, N, N, N, N, N, N, N,
|
|
} };
|
|
|
|
static const struct opcode opcode_table[256] = {
|
|
/* 0x00 - 0x07 */
|
|
F6ALU(Lock, em_add),
|
|
I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
|
|
I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
|
|
/* 0x08 - 0x0F */
|
|
F6ALU(Lock | PageTable, em_or),
|
|
I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
|
|
N,
|
|
/* 0x10 - 0x17 */
|
|
F6ALU(Lock, em_adc),
|
|
I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
|
|
I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
|
|
/* 0x18 - 0x1F */
|
|
F6ALU(Lock, em_sbb),
|
|
I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
|
|
I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
|
|
/* 0x20 - 0x27 */
|
|
F6ALU(Lock | PageTable, em_and), N, N,
|
|
/* 0x28 - 0x2F */
|
|
F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
|
|
/* 0x30 - 0x37 */
|
|
F6ALU(Lock, em_xor), N, N,
|
|
/* 0x38 - 0x3F */
|
|
F6ALU(NoWrite, em_cmp), N, N,
|
|
/* 0x40 - 0x4F */
|
|
X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
|
|
/* 0x50 - 0x57 */
|
|
X8(I(SrcReg | Stack, em_push)),
|
|
/* 0x58 - 0x5F */
|
|
X8(I(DstReg | Stack, em_pop)),
|
|
/* 0x60 - 0x67 */
|
|
I(ImplicitOps | Stack | No64, em_pusha),
|
|
I(ImplicitOps | Stack | No64, em_popa),
|
|
N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
|
|
N, N, N, N,
|
|
/* 0x68 - 0x6F */
|
|
I(SrcImm | Mov | Stack, em_push),
|
|
I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
|
|
I(SrcImmByte | Mov | Stack, em_push),
|
|
I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
|
|
I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
|
|
I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
|
|
/* 0x70 - 0x7F */
|
|
X16(D(SrcImmByte)),
|
|
/* 0x80 - 0x87 */
|
|
G(ByteOp | DstMem | SrcImm, group1),
|
|
G(DstMem | SrcImm, group1),
|
|
G(ByteOp | DstMem | SrcImm | No64, group1),
|
|
G(DstMem | SrcImmByte, group1),
|
|
F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
|
|
I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
|
|
/* 0x88 - 0x8F */
|
|
I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
|
|
I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
|
|
I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
|
|
D(ModRM | SrcMem | NoAccess | DstReg),
|
|
I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
|
|
G(0, group1A),
|
|
/* 0x90 - 0x97 */
|
|
DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
|
|
/* 0x98 - 0x9F */
|
|
D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
|
|
I(SrcImmFAddr | No64, em_call_far), N,
|
|
II(ImplicitOps | Stack, em_pushf, pushf),
|
|
II(ImplicitOps | Stack, em_popf, popf),
|
|
I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
|
|
/* 0xA0 - 0xA7 */
|
|
I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
|
|
I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
|
|
I2bv(SrcSI | DstDI | Mov | String, em_mov),
|
|
F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
|
|
/* 0xA8 - 0xAF */
|
|
F2bv(DstAcc | SrcImm | NoWrite, em_test),
|
|
I2bv(SrcAcc | DstDI | Mov | String, em_mov),
|
|
I2bv(SrcSI | DstAcc | Mov | String, em_mov),
|
|
F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
|
|
/* 0xB0 - 0xB7 */
|
|
X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
|
|
/* 0xB8 - 0xBF */
|
|
X8(I(DstReg | SrcImm64 | Mov, em_mov)),
|
|
/* 0xC0 - 0xC7 */
|
|
G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
|
|
I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
|
|
I(ImplicitOps | Stack, em_ret),
|
|
I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
|
|
I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
|
|
G(ByteOp, group11), G(0, group11),
|
|
/* 0xC8 - 0xCF */
|
|
I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
|
|
I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
|
|
I(ImplicitOps | Stack, em_ret_far),
|
|
D(ImplicitOps), DI(SrcImmByte, intn),
|
|
D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
|
|
/* 0xD0 - 0xD7 */
|
|
G(Src2One | ByteOp, group2), G(Src2One, group2),
|
|
G(Src2CL | ByteOp, group2), G(Src2CL, group2),
|
|
I(DstAcc | SrcImmUByte | No64, em_aam),
|
|
I(DstAcc | SrcImmUByte | No64, em_aad),
|
|
F(DstAcc | ByteOp | No64, em_salc),
|
|
I(DstAcc | SrcXLat | ByteOp, em_mov),
|
|
/* 0xD8 - 0xDF */
|
|
N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
|
|
/* 0xE0 - 0xE7 */
|
|
X3(I(SrcImmByte, em_loop)),
|
|
I(SrcImmByte, em_jcxz),
|
|
I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
|
|
I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
|
|
/* 0xE8 - 0xEF */
|
|
I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
|
|
I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
|
|
I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
|
|
I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
|
|
/* 0xF0 - 0xF7 */
|
|
N, DI(ImplicitOps, icebp), N, N,
|
|
DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
|
|
G(ByteOp, group3), G(0, group3),
|
|
/* 0xF8 - 0xFF */
|
|
D(ImplicitOps), D(ImplicitOps),
|
|
I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
|
|
D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
|
|
};
|
|
|
|
static const struct opcode twobyte_table[256] = {
|
|
/* 0x00 - 0x0F */
|
|
G(0, group6), GD(0, &group7), N, N,
|
|
N, I(ImplicitOps | EmulateOnUD, em_syscall),
|
|
II(ImplicitOps | Priv, em_clts, clts), N,
|
|
DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
|
|
N, D(ImplicitOps | ModRM), N, N,
|
|
/* 0x10 - 0x1F */
|
|
N, N, N, N, N, N, N, N,
|
|
D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM),
|
|
/* 0x20 - 0x2F */
|
|
DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
|
|
DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
|
|
IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
|
|
IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
|
|
N, N, N, N,
|
|
GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
|
|
GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
|
|
N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
|
|
N, N, N, N,
|
|
/* 0x30 - 0x3F */
|
|
II(ImplicitOps | Priv, em_wrmsr, wrmsr),
|
|
IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
|
|
II(ImplicitOps | Priv, em_rdmsr, rdmsr),
|
|
IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
|
|
I(ImplicitOps | EmulateOnUD, em_sysenter),
|
|
I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
|
|
N, N,
|
|
N, N, N, N, N, N, N, N,
|
|
/* 0x40 - 0x4F */
|
|
X16(D(DstReg | SrcMem | ModRM | Mov)),
|
|
/* 0x50 - 0x5F */
|
|
N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
|
|
/* 0x60 - 0x6F */
|
|
N, N, N, N,
|
|
N, N, N, N,
|
|
N, N, N, N,
|
|
N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
|
|
/* 0x70 - 0x7F */
|
|
N, N, N, N,
|
|
N, N, N, N,
|
|
N, N, N, N,
|
|
N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
|
|
/* 0x80 - 0x8F */
|
|
X16(D(SrcImm)),
|
|
/* 0x90 - 0x9F */
|
|
X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
|
|
/* 0xA0 - 0xA7 */
|
|
I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
|
|
II(ImplicitOps, em_cpuid, cpuid),
|
|
F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
|
|
F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
|
|
F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
|
|
/* 0xA8 - 0xAF */
|
|
I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
|
|
DI(ImplicitOps, rsm),
|
|
F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
|
|
F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
|
|
F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
|
|
D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
|
|
/* 0xB0 - 0xB7 */
|
|
I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
|
|
I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
|
|
F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
|
|
I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
|
|
I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
|
|
D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
|
|
/* 0xB8 - 0xBF */
|
|
N, N,
|
|
G(BitOp, group8),
|
|
F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
|
|
F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
|
|
D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
|
|
/* 0xC0 - 0xC7 */
|
|
F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
|
|
N, D(DstMem | SrcReg | ModRM | Mov),
|
|
N, N, N, GD(0, &group9),
|
|
/* 0xC8 - 0xCF */
|
|
X8(I(DstReg, em_bswap)),
|
|
/* 0xD0 - 0xDF */
|
|
N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
|
|
/* 0xE0 - 0xEF */
|
|
N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
|
|
/* 0xF0 - 0xFF */
|
|
N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
|
|
};
|
|
|
|
static const struct gprefix three_byte_0f_38_f0 = {
|
|
I(DstReg | SrcMem | Mov, em_movbe), N, N, N
|
|
};
|
|
|
|
static const struct gprefix three_byte_0f_38_f1 = {
|
|
I(DstMem | SrcReg | Mov, em_movbe), N, N, N
|
|
};
|
|
|
|
/*
|
|
* Insns below are selected by the prefix which indexed by the third opcode
|
|
* byte.
|
|
*/
|
|
static const struct opcode opcode_map_0f_38[256] = {
|
|
/* 0x00 - 0x7f */
|
|
X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
|
|
/* 0x80 - 0xef */
|
|
X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
|
|
/* 0xf0 - 0xf1 */
|
|
GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
|
|
GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
|
|
/* 0xf2 - 0xff */
|
|
N, N, X4(N), X8(N)
|
|
};
|
|
|
|
#undef D
|
|
#undef N
|
|
#undef G
|
|
#undef GD
|
|
#undef I
|
|
#undef GP
|
|
#undef EXT
|
|
|
|
#undef D2bv
|
|
#undef D2bvIP
|
|
#undef I2bv
|
|
#undef I2bvIP
|
|
#undef I6ALU
|
|
|
|
static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
unsigned size;
|
|
|
|
size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
|
|
if (size == 8)
|
|
size = 4;
|
|
return size;
|
|
}
|
|
|
|
static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
|
|
unsigned size, bool sign_extension)
|
|
{
|
|
int rc = X86EMUL_CONTINUE;
|
|
|
|
op->type = OP_IMM;
|
|
op->bytes = size;
|
|
op->addr.mem.ea = ctxt->_eip;
|
|
/* NB. Immediates are sign-extended as necessary. */
|
|
switch (op->bytes) {
|
|
case 1:
|
|
op->val = insn_fetch(s8, ctxt);
|
|
break;
|
|
case 2:
|
|
op->val = insn_fetch(s16, ctxt);
|
|
break;
|
|
case 4:
|
|
op->val = insn_fetch(s32, ctxt);
|
|
break;
|
|
case 8:
|
|
op->val = insn_fetch(s64, ctxt);
|
|
break;
|
|
}
|
|
if (!sign_extension) {
|
|
switch (op->bytes) {
|
|
case 1:
|
|
op->val &= 0xff;
|
|
break;
|
|
case 2:
|
|
op->val &= 0xffff;
|
|
break;
|
|
case 4:
|
|
op->val &= 0xffffffff;
|
|
break;
|
|
}
|
|
}
|
|
done:
|
|
return rc;
|
|
}
|
|
|
|
static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
|
|
unsigned d)
|
|
{
|
|
int rc = X86EMUL_CONTINUE;
|
|
|
|
switch (d) {
|
|
case OpReg:
|
|
decode_register_operand(ctxt, op);
|
|
break;
|
|
case OpImmUByte:
|
|
rc = decode_imm(ctxt, op, 1, false);
|
|
break;
|
|
case OpMem:
|
|
ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
|
|
mem_common:
|
|
*op = ctxt->memop;
|
|
ctxt->memopp = op;
|
|
if ((ctxt->d & BitOp) && op == &ctxt->dst)
|
|
fetch_bit_operand(ctxt);
|
|
op->orig_val = op->val;
|
|
break;
|
|
case OpMem64:
|
|
ctxt->memop.bytes = 8;
|
|
goto mem_common;
|
|
case OpAcc:
|
|
op->type = OP_REG;
|
|
op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
|
|
op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
|
|
fetch_register_operand(op);
|
|
op->orig_val = op->val;
|
|
break;
|
|
case OpAccLo:
|
|
op->type = OP_REG;
|
|
op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
|
|
op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
|
|
fetch_register_operand(op);
|
|
op->orig_val = op->val;
|
|
break;
|
|
case OpAccHi:
|
|
if (ctxt->d & ByteOp) {
|
|
op->type = OP_NONE;
|
|
break;
|
|
}
|
|
op->type = OP_REG;
|
|
op->bytes = ctxt->op_bytes;
|
|
op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
|
|
fetch_register_operand(op);
|
|
op->orig_val = op->val;
|
|
break;
|
|
case OpDI:
|
|
op->type = OP_MEM;
|
|
op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
|
|
op->addr.mem.ea =
|
|
register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
|
|
op->addr.mem.seg = VCPU_SREG_ES;
|
|
op->val = 0;
|
|
op->count = 1;
|
|
break;
|
|
case OpDX:
|
|
op->type = OP_REG;
|
|
op->bytes = 2;
|
|
op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
|
|
fetch_register_operand(op);
|
|
break;
|
|
case OpCL:
|
|
op->bytes = 1;
|
|
op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
|
|
break;
|
|
case OpImmByte:
|
|
rc = decode_imm(ctxt, op, 1, true);
|
|
break;
|
|
case OpOne:
|
|
op->bytes = 1;
|
|
op->val = 1;
|
|
break;
|
|
case OpImm:
|
|
rc = decode_imm(ctxt, op, imm_size(ctxt), true);
|
|
break;
|
|
case OpImm64:
|
|
rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
|
|
break;
|
|
case OpMem8:
|
|
ctxt->memop.bytes = 1;
|
|
if (ctxt->memop.type == OP_REG) {
|
|
ctxt->memop.addr.reg = decode_register(ctxt,
|
|
ctxt->modrm_rm, true);
|
|
fetch_register_operand(&ctxt->memop);
|
|
}
|
|
goto mem_common;
|
|
case OpMem16:
|
|
ctxt->memop.bytes = 2;
|
|
goto mem_common;
|
|
case OpMem32:
|
|
ctxt->memop.bytes = 4;
|
|
goto mem_common;
|
|
case OpImmU16:
|
|
rc = decode_imm(ctxt, op, 2, false);
|
|
break;
|
|
case OpImmU:
|
|
rc = decode_imm(ctxt, op, imm_size(ctxt), false);
|
|
break;
|
|
case OpSI:
|
|
op->type = OP_MEM;
|
|
op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
|
|
op->addr.mem.ea =
|
|
register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
|
|
op->addr.mem.seg = seg_override(ctxt);
|
|
op->val = 0;
|
|
op->count = 1;
|
|
break;
|
|
case OpXLat:
|
|
op->type = OP_MEM;
|
|
op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
|
|
op->addr.mem.ea =
|
|
register_address(ctxt,
|
|
reg_read(ctxt, VCPU_REGS_RBX) +
|
|
(reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
|
|
op->addr.mem.seg = seg_override(ctxt);
|
|
op->val = 0;
|
|
break;
|
|
case OpImmFAddr:
|
|
op->type = OP_IMM;
|
|
op->addr.mem.ea = ctxt->_eip;
|
|
op->bytes = ctxt->op_bytes + 2;
|
|
insn_fetch_arr(op->valptr, op->bytes, ctxt);
|
|
break;
|
|
case OpMemFAddr:
|
|
ctxt->memop.bytes = ctxt->op_bytes + 2;
|
|
goto mem_common;
|
|
case OpES:
|
|
op->val = VCPU_SREG_ES;
|
|
break;
|
|
case OpCS:
|
|
op->val = VCPU_SREG_CS;
|
|
break;
|
|
case OpSS:
|
|
op->val = VCPU_SREG_SS;
|
|
break;
|
|
case OpDS:
|
|
op->val = VCPU_SREG_DS;
|
|
break;
|
|
case OpFS:
|
|
op->val = VCPU_SREG_FS;
|
|
break;
|
|
case OpGS:
|
|
op->val = VCPU_SREG_GS;
|
|
break;
|
|
case OpImplicit:
|
|
/* Special instructions do their own operand decoding. */
|
|
default:
|
|
op->type = OP_NONE; /* Disable writeback. */
|
|
break;
|
|
}
|
|
|
|
done:
|
|
return rc;
|
|
}
|
|
|
|
int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
|
|
{
|
|
int rc = X86EMUL_CONTINUE;
|
|
int mode = ctxt->mode;
|
|
int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
|
|
bool op_prefix = false;
|
|
struct opcode opcode;
|
|
|
|
ctxt->memop.type = OP_NONE;
|
|
ctxt->memopp = NULL;
|
|
ctxt->_eip = ctxt->eip;
|
|
ctxt->fetch.start = ctxt->_eip;
|
|
ctxt->fetch.end = ctxt->fetch.start + insn_len;
|
|
ctxt->opcode_len = 1;
|
|
if (insn_len > 0)
|
|
memcpy(ctxt->fetch.data, insn, insn_len);
|
|
|
|
switch (mode) {
|
|
case X86EMUL_MODE_REAL:
|
|
case X86EMUL_MODE_VM86:
|
|
case X86EMUL_MODE_PROT16:
|
|
def_op_bytes = def_ad_bytes = 2;
|
|
break;
|
|
case X86EMUL_MODE_PROT32:
|
|
def_op_bytes = def_ad_bytes = 4;
|
|
break;
|
|
#ifdef CONFIG_X86_64
|
|
case X86EMUL_MODE_PROT64:
|
|
def_op_bytes = 4;
|
|
def_ad_bytes = 8;
|
|
break;
|
|
#endif
|
|
default:
|
|
return EMULATION_FAILED;
|
|
}
|
|
|
|
ctxt->op_bytes = def_op_bytes;
|
|
ctxt->ad_bytes = def_ad_bytes;
|
|
|
|
/* Legacy prefixes. */
|
|
for (;;) {
|
|
switch (ctxt->b = insn_fetch(u8, ctxt)) {
|
|
case 0x66: /* operand-size override */
|
|
op_prefix = true;
|
|
/* switch between 2/4 bytes */
|
|
ctxt->op_bytes = def_op_bytes ^ 6;
|
|
break;
|
|
case 0x67: /* address-size override */
|
|
if (mode == X86EMUL_MODE_PROT64)
|
|
/* switch between 4/8 bytes */
|
|
ctxt->ad_bytes = def_ad_bytes ^ 12;
|
|
else
|
|
/* switch between 2/4 bytes */
|
|
ctxt->ad_bytes = def_ad_bytes ^ 6;
|
|
break;
|
|
case 0x26: /* ES override */
|
|
case 0x2e: /* CS override */
|
|
case 0x36: /* SS override */
|
|
case 0x3e: /* DS override */
|
|
set_seg_override(ctxt, (ctxt->b >> 3) & 3);
|
|
break;
|
|
case 0x64: /* FS override */
|
|
case 0x65: /* GS override */
|
|
set_seg_override(ctxt, ctxt->b & 7);
|
|
break;
|
|
case 0x40 ... 0x4f: /* REX */
|
|
if (mode != X86EMUL_MODE_PROT64)
|
|
goto done_prefixes;
|
|
ctxt->rex_prefix = ctxt->b;
|
|
continue;
|
|
case 0xf0: /* LOCK */
|
|
ctxt->lock_prefix = 1;
|
|
break;
|
|
case 0xf2: /* REPNE/REPNZ */
|
|
case 0xf3: /* REP/REPE/REPZ */
|
|
ctxt->rep_prefix = ctxt->b;
|
|
break;
|
|
default:
|
|
goto done_prefixes;
|
|
}
|
|
|
|
/* Any legacy prefix after a REX prefix nullifies its effect. */
|
|
|
|
ctxt->rex_prefix = 0;
|
|
}
|
|
|
|
done_prefixes:
|
|
|
|
/* REX prefix. */
|
|
if (ctxt->rex_prefix & 8)
|
|
ctxt->op_bytes = 8; /* REX.W */
|
|
|
|
/* Opcode byte(s). */
|
|
opcode = opcode_table[ctxt->b];
|
|
/* Two-byte opcode? */
|
|
if (ctxt->b == 0x0f) {
|
|
ctxt->opcode_len = 2;
|
|
ctxt->b = insn_fetch(u8, ctxt);
|
|
opcode = twobyte_table[ctxt->b];
|
|
|
|
/* 0F_38 opcode map */
|
|
if (ctxt->b == 0x38) {
|
|
ctxt->opcode_len = 3;
|
|
ctxt->b = insn_fetch(u8, ctxt);
|
|
opcode = opcode_map_0f_38[ctxt->b];
|
|
}
|
|
}
|
|
ctxt->d = opcode.flags;
|
|
|
|
if (ctxt->d & ModRM)
|
|
ctxt->modrm = insn_fetch(u8, ctxt);
|
|
|
|
while (ctxt->d & GroupMask) {
|
|
switch (ctxt->d & GroupMask) {
|
|
case Group:
|
|
goffset = (ctxt->modrm >> 3) & 7;
|
|
opcode = opcode.u.group[goffset];
|
|
break;
|
|
case GroupDual:
|
|
goffset = (ctxt->modrm >> 3) & 7;
|
|
if ((ctxt->modrm >> 6) == 3)
|
|
opcode = opcode.u.gdual->mod3[goffset];
|
|
else
|
|
opcode = opcode.u.gdual->mod012[goffset];
|
|
break;
|
|
case RMExt:
|
|
goffset = ctxt->modrm & 7;
|
|
opcode = opcode.u.group[goffset];
|
|
break;
|
|
case Prefix:
|
|
if (ctxt->rep_prefix && op_prefix)
|
|
return EMULATION_FAILED;
|
|
simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
|
|
switch (simd_prefix) {
|
|
case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
|
|
case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
|
|
case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
|
|
case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
|
|
}
|
|
break;
|
|
case Escape:
|
|
if (ctxt->modrm > 0xbf)
|
|
opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
|
|
else
|
|
opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
|
|
break;
|
|
default:
|
|
return EMULATION_FAILED;
|
|
}
|
|
|
|
ctxt->d &= ~(u64)GroupMask;
|
|
ctxt->d |= opcode.flags;
|
|
}
|
|
|
|
ctxt->execute = opcode.u.execute;
|
|
ctxt->check_perm = opcode.check_perm;
|
|
ctxt->intercept = opcode.intercept;
|
|
|
|
/* Unrecognised? */
|
|
if (ctxt->d == 0 || (ctxt->d & NotImpl))
|
|
return EMULATION_FAILED;
|
|
|
|
if (!(ctxt->d & EmulateOnUD) && ctxt->ud)
|
|
return EMULATION_FAILED;
|
|
|
|
if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
|
|
ctxt->op_bytes = 8;
|
|
|
|
if (ctxt->d & Op3264) {
|
|
if (mode == X86EMUL_MODE_PROT64)
|
|
ctxt->op_bytes = 8;
|
|
else
|
|
ctxt->op_bytes = 4;
|
|
}
|
|
|
|
if (ctxt->d & Sse)
|
|
ctxt->op_bytes = 16;
|
|
else if (ctxt->d & Mmx)
|
|
ctxt->op_bytes = 8;
|
|
|
|
/* ModRM and SIB bytes. */
|
|
if (ctxt->d & ModRM) {
|
|
rc = decode_modrm(ctxt, &ctxt->memop);
|
|
if (!ctxt->has_seg_override)
|
|
set_seg_override(ctxt, ctxt->modrm_seg);
|
|
} else if (ctxt->d & MemAbs)
|
|
rc = decode_abs(ctxt, &ctxt->memop);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
goto done;
|
|
|
|
if (!ctxt->has_seg_override)
|
|
set_seg_override(ctxt, VCPU_SREG_DS);
|
|
|
|
ctxt->memop.addr.mem.seg = seg_override(ctxt);
|
|
|
|
if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
|
|
ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
|
|
|
|
/*
|
|
* Decode and fetch the source operand: register, memory
|
|
* or immediate.
|
|
*/
|
|
rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
goto done;
|
|
|
|
/*
|
|
* Decode and fetch the second source operand: register, memory
|
|
* or immediate.
|
|
*/
|
|
rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
goto done;
|
|
|
|
/* Decode and fetch the destination operand: register or memory. */
|
|
rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
|
|
|
|
done:
|
|
if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
|
|
ctxt->memopp->addr.mem.ea += ctxt->_eip;
|
|
|
|
return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
|
|
}
|
|
|
|
bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
return ctxt->d & PageTable;
|
|
}
|
|
|
|
static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
/* The second termination condition only applies for REPE
|
|
* and REPNE. Test if the repeat string operation prefix is
|
|
* REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
|
|
* corresponding termination condition according to:
|
|
* - if REPE/REPZ and ZF = 0 then done
|
|
* - if REPNE/REPNZ and ZF = 1 then done
|
|
*/
|
|
if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
|
|
(ctxt->b == 0xae) || (ctxt->b == 0xaf))
|
|
&& (((ctxt->rep_prefix == REPE_PREFIX) &&
|
|
((ctxt->eflags & EFLG_ZF) == 0))
|
|
|| ((ctxt->rep_prefix == REPNE_PREFIX) &&
|
|
((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
bool fault = false;
|
|
|
|
ctxt->ops->get_fpu(ctxt);
|
|
asm volatile("1: fwait \n\t"
|
|
"2: \n\t"
|
|
".pushsection .fixup,\"ax\" \n\t"
|
|
"3: \n\t"
|
|
"movb $1, %[fault] \n\t"
|
|
"jmp 2b \n\t"
|
|
".popsection \n\t"
|
|
_ASM_EXTABLE(1b, 3b)
|
|
: [fault]"+qm"(fault));
|
|
ctxt->ops->put_fpu(ctxt);
|
|
|
|
if (unlikely(fault))
|
|
return emulate_exception(ctxt, MF_VECTOR, 0, false);
|
|
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
|
|
struct operand *op)
|
|
{
|
|
if (op->type == OP_MM)
|
|
read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
|
|
}
|
|
|
|
static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
|
|
{
|
|
ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
|
|
if (!(ctxt->d & ByteOp))
|
|
fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
|
|
asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
|
|
: "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
|
|
[fastop]"+S"(fop)
|
|
: "c"(ctxt->src2.val));
|
|
ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
|
|
if (!fop) /* exception is returned in fop variable */
|
|
return emulate_de(ctxt);
|
|
return X86EMUL_CONTINUE;
|
|
}
|
|
|
|
int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
const struct x86_emulate_ops *ops = ctxt->ops;
|
|
int rc = X86EMUL_CONTINUE;
|
|
int saved_dst_type = ctxt->dst.type;
|
|
|
|
ctxt->mem_read.pos = 0;
|
|
|
|
if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
|
|
(ctxt->d & Undefined)) {
|
|
rc = emulate_ud(ctxt);
|
|
goto done;
|
|
}
|
|
|
|
/* LOCK prefix is allowed only with some instructions */
|
|
if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
|
|
rc = emulate_ud(ctxt);
|
|
goto done;
|
|
}
|
|
|
|
if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
|
|
rc = emulate_ud(ctxt);
|
|
goto done;
|
|
}
|
|
|
|
if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
|
|
|| ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
|
|
rc = emulate_ud(ctxt);
|
|
goto done;
|
|
}
|
|
|
|
if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
|
|
rc = emulate_nm(ctxt);
|
|
goto done;
|
|
}
|
|
|
|
if (ctxt->d & Mmx) {
|
|
rc = flush_pending_x87_faults(ctxt);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
goto done;
|
|
/*
|
|
* Now that we know the fpu is exception safe, we can fetch
|
|
* operands from it.
|
|
*/
|
|
fetch_possible_mmx_operand(ctxt, &ctxt->src);
|
|
fetch_possible_mmx_operand(ctxt, &ctxt->src2);
|
|
if (!(ctxt->d & Mov))
|
|
fetch_possible_mmx_operand(ctxt, &ctxt->dst);
|
|
}
|
|
|
|
if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
|
|
rc = emulator_check_intercept(ctxt, ctxt->intercept,
|
|
X86_ICPT_PRE_EXCEPT);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
goto done;
|
|
}
|
|
|
|
/* Privileged instruction can be executed only in CPL=0 */
|
|
if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
|
|
rc = emulate_gp(ctxt, 0);
|
|
goto done;
|
|
}
|
|
|
|
/* Instruction can only be executed in protected mode */
|
|
if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
|
|
rc = emulate_ud(ctxt);
|
|
goto done;
|
|
}
|
|
|
|
/* Do instruction specific permission checks */
|
|
if (ctxt->check_perm) {
|
|
rc = ctxt->check_perm(ctxt);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
goto done;
|
|
}
|
|
|
|
if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
|
|
rc = emulator_check_intercept(ctxt, ctxt->intercept,
|
|
X86_ICPT_POST_EXCEPT);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
goto done;
|
|
}
|
|
|
|
if (ctxt->rep_prefix && (ctxt->d & String)) {
|
|
/* All REP prefixes have the same first termination condition */
|
|
if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
|
|
ctxt->eip = ctxt->_eip;
|
|
goto done;
|
|
}
|
|
}
|
|
|
|
if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
|
|
rc = segmented_read(ctxt, ctxt->src.addr.mem,
|
|
ctxt->src.valptr, ctxt->src.bytes);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
goto done;
|
|
ctxt->src.orig_val64 = ctxt->src.val64;
|
|
}
|
|
|
|
if (ctxt->src2.type == OP_MEM) {
|
|
rc = segmented_read(ctxt, ctxt->src2.addr.mem,
|
|
&ctxt->src2.val, ctxt->src2.bytes);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
goto done;
|
|
}
|
|
|
|
if ((ctxt->d & DstMask) == ImplicitOps)
|
|
goto special_insn;
|
|
|
|
|
|
if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
|
|
/* optimisation - avoid slow emulated read if Mov */
|
|
rc = segmented_read(ctxt, ctxt->dst.addr.mem,
|
|
&ctxt->dst.val, ctxt->dst.bytes);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
goto done;
|
|
}
|
|
ctxt->dst.orig_val = ctxt->dst.val;
|
|
|
|
special_insn:
|
|
|
|
if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
|
|
rc = emulator_check_intercept(ctxt, ctxt->intercept,
|
|
X86_ICPT_POST_MEMACCESS);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
goto done;
|
|
}
|
|
|
|
if (ctxt->execute) {
|
|
if (ctxt->d & Fastop) {
|
|
void (*fop)(struct fastop *) = (void *)ctxt->execute;
|
|
rc = fastop(ctxt, fop);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
goto done;
|
|
goto writeback;
|
|
}
|
|
rc = ctxt->execute(ctxt);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
goto done;
|
|
goto writeback;
|
|
}
|
|
|
|
if (ctxt->opcode_len == 2)
|
|
goto twobyte_insn;
|
|
else if (ctxt->opcode_len == 3)
|
|
goto threebyte_insn;
|
|
|
|
switch (ctxt->b) {
|
|
case 0x63: /* movsxd */
|
|
if (ctxt->mode != X86EMUL_MODE_PROT64)
|
|
goto cannot_emulate;
|
|
ctxt->dst.val = (s32) ctxt->src.val;
|
|
break;
|
|
case 0x70 ... 0x7f: /* jcc (short) */
|
|
if (test_cc(ctxt->b, ctxt->eflags))
|
|
jmp_rel(ctxt, ctxt->src.val);
|
|
break;
|
|
case 0x8d: /* lea r16/r32, m */
|
|
ctxt->dst.val = ctxt->src.addr.mem.ea;
|
|
break;
|
|
case 0x90 ... 0x97: /* nop / xchg reg, rax */
|
|
if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
|
|
break;
|
|
rc = em_xchg(ctxt);
|
|
break;
|
|
case 0x98: /* cbw/cwde/cdqe */
|
|
switch (ctxt->op_bytes) {
|
|
case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
|
|
case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
|
|
case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
|
|
}
|
|
break;
|
|
case 0xcc: /* int3 */
|
|
rc = emulate_int(ctxt, 3);
|
|
break;
|
|
case 0xcd: /* int n */
|
|
rc = emulate_int(ctxt, ctxt->src.val);
|
|
break;
|
|
case 0xce: /* into */
|
|
if (ctxt->eflags & EFLG_OF)
|
|
rc = emulate_int(ctxt, 4);
|
|
break;
|
|
case 0xe9: /* jmp rel */
|
|
case 0xeb: /* jmp rel short */
|
|
jmp_rel(ctxt, ctxt->src.val);
|
|
ctxt->dst.type = OP_NONE; /* Disable writeback. */
|
|
break;
|
|
case 0xf4: /* hlt */
|
|
ctxt->ops->halt(ctxt);
|
|
break;
|
|
case 0xf5: /* cmc */
|
|
/* complement carry flag from eflags reg */
|
|
ctxt->eflags ^= EFLG_CF;
|
|
break;
|
|
case 0xf8: /* clc */
|
|
ctxt->eflags &= ~EFLG_CF;
|
|
break;
|
|
case 0xf9: /* stc */
|
|
ctxt->eflags |= EFLG_CF;
|
|
break;
|
|
case 0xfc: /* cld */
|
|
ctxt->eflags &= ~EFLG_DF;
|
|
break;
|
|
case 0xfd: /* std */
|
|
ctxt->eflags |= EFLG_DF;
|
|
break;
|
|
default:
|
|
goto cannot_emulate;
|
|
}
|
|
|
|
if (rc != X86EMUL_CONTINUE)
|
|
goto done;
|
|
|
|
writeback:
|
|
if (!(ctxt->d & NoWrite)) {
|
|
rc = writeback(ctxt, &ctxt->dst);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
goto done;
|
|
}
|
|
if (ctxt->d & SrcWrite) {
|
|
BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
|
|
rc = writeback(ctxt, &ctxt->src);
|
|
if (rc != X86EMUL_CONTINUE)
|
|
goto done;
|
|
}
|
|
|
|
/*
|
|
* restore dst type in case the decoding will be reused
|
|
* (happens for string instruction )
|
|
*/
|
|
ctxt->dst.type = saved_dst_type;
|
|
|
|
if ((ctxt->d & SrcMask) == SrcSI)
|
|
string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
|
|
|
|
if ((ctxt->d & DstMask) == DstDI)
|
|
string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
|
|
|
|
if (ctxt->rep_prefix && (ctxt->d & String)) {
|
|
unsigned int count;
|
|
struct read_cache *r = &ctxt->io_read;
|
|
if ((ctxt->d & SrcMask) == SrcSI)
|
|
count = ctxt->src.count;
|
|
else
|
|
count = ctxt->dst.count;
|
|
register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
|
|
-count);
|
|
|
|
if (!string_insn_completed(ctxt)) {
|
|
/*
|
|
* Re-enter guest when pio read ahead buffer is empty
|
|
* or, if it is not used, after each 1024 iteration.
|
|
*/
|
|
if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
|
|
(r->end == 0 || r->end != r->pos)) {
|
|
/*
|
|
* Reset read cache. Usually happens before
|
|
* decode, but since instruction is restarted
|
|
* we have to do it here.
|
|
*/
|
|
ctxt->mem_read.end = 0;
|
|
writeback_registers(ctxt);
|
|
return EMULATION_RESTART;
|
|
}
|
|
goto done; /* skip rip writeback */
|
|
}
|
|
}
|
|
|
|
ctxt->eip = ctxt->_eip;
|
|
|
|
done:
|
|
if (rc == X86EMUL_PROPAGATE_FAULT)
|
|
ctxt->have_exception = true;
|
|
if (rc == X86EMUL_INTERCEPTED)
|
|
return EMULATION_INTERCEPTED;
|
|
|
|
if (rc == X86EMUL_CONTINUE)
|
|
writeback_registers(ctxt);
|
|
|
|
return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
|
|
|
|
twobyte_insn:
|
|
switch (ctxt->b) {
|
|
case 0x09: /* wbinvd */
|
|
(ctxt->ops->wbinvd)(ctxt);
|
|
break;
|
|
case 0x08: /* invd */
|
|
case 0x0d: /* GrpP (prefetch) */
|
|
case 0x18: /* Grp16 (prefetch/nop) */
|
|
case 0x1f: /* nop */
|
|
break;
|
|
case 0x20: /* mov cr, reg */
|
|
ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
|
|
break;
|
|
case 0x21: /* mov from dr to reg */
|
|
ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
|
|
break;
|
|
case 0x40 ... 0x4f: /* cmov */
|
|
ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
|
|
if (!test_cc(ctxt->b, ctxt->eflags))
|
|
ctxt->dst.type = OP_NONE; /* no writeback */
|
|
break;
|
|
case 0x80 ... 0x8f: /* jnz rel, etc*/
|
|
if (test_cc(ctxt->b, ctxt->eflags))
|
|
jmp_rel(ctxt, ctxt->src.val);
|
|
break;
|
|
case 0x90 ... 0x9f: /* setcc r/m8 */
|
|
ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
|
|
break;
|
|
case 0xae: /* clflush */
|
|
break;
|
|
case 0xb6 ... 0xb7: /* movzx */
|
|
ctxt->dst.bytes = ctxt->op_bytes;
|
|
ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
|
|
: (u16) ctxt->src.val;
|
|
break;
|
|
case 0xbe ... 0xbf: /* movsx */
|
|
ctxt->dst.bytes = ctxt->op_bytes;
|
|
ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
|
|
(s16) ctxt->src.val;
|
|
break;
|
|
case 0xc3: /* movnti */
|
|
ctxt->dst.bytes = ctxt->op_bytes;
|
|
ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
|
|
(u64) ctxt->src.val;
|
|
break;
|
|
default:
|
|
goto cannot_emulate;
|
|
}
|
|
|
|
threebyte_insn:
|
|
|
|
if (rc != X86EMUL_CONTINUE)
|
|
goto done;
|
|
|
|
goto writeback;
|
|
|
|
cannot_emulate:
|
|
return EMULATION_FAILED;
|
|
}
|
|
|
|
void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
invalidate_registers(ctxt);
|
|
}
|
|
|
|
void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
writeback_registers(ctxt);
|
|
}
|