mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 09:46:50 +07:00
bb693f13a0
The last user of set_pmd_pfn() went away in commit f03574f2d5, so this
has been dead code for over a year.
Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
arch/x86/include/asm/pgtable_32.h | 3 ---
arch/x86/mm/pgtable_32.c | 35 -----------------------------------
2 files changed, 38 deletions(-)
79 lines
2.0 KiB
C
79 lines
2.0 KiB
C
#ifndef _ASM_X86_PGTABLE_32_H
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#define _ASM_X86_PGTABLE_32_H
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#include <asm/pgtable_32_types.h>
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/*
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* The Linux memory management assumes a three-level page table setup. On
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* the i386, we use that, but "fold" the mid level into the top-level page
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* table, so that we physically have the same two-level page table as the
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* i386 mmu expects.
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*
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* This file contains the functions and defines necessary to modify and use
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* the i386 page table tree.
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*/
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#ifndef __ASSEMBLY__
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#include <asm/processor.h>
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#include <asm/fixmap.h>
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#include <linux/threads.h>
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#include <asm/paravirt.h>
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#include <linux/bitops.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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struct mm_struct;
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struct vm_area_struct;
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extern pgd_t swapper_pg_dir[1024];
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extern pgd_t initial_page_table[1024];
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static inline void pgtable_cache_init(void) { }
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static inline void check_pgt_cache(void) { }
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void paging_init(void);
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/*
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* Define this if things work differently on an i386 and an i486:
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* it will (on an i486) warn about kernel memory accesses that are
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* done without a 'access_ok(VERIFY_WRITE,..)'
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*/
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#undef TEST_ACCESS_OK
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#ifdef CONFIG_X86_PAE
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# include <asm/pgtable-3level.h>
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#else
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# include <asm/pgtable-2level.h>
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#endif
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#if defined(CONFIG_HIGHPTE)
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#define pte_offset_map(dir, address) \
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((pte_t *)kmap_atomic(pmd_page(*(dir))) + \
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pte_index((address)))
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#define pte_unmap(pte) kunmap_atomic((pte))
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#else
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#define pte_offset_map(dir, address) \
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((pte_t *)page_address(pmd_page(*(dir))) + pte_index((address)))
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#define pte_unmap(pte) do { } while (0)
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#endif
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/* Clear a kernel PTE and flush it from the TLB */
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#define kpte_clear_flush(ptep, vaddr) \
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do { \
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pte_clear(&init_mm, (vaddr), (ptep)); \
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__flush_tlb_one((vaddr)); \
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} while (0)
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#endif /* !__ASSEMBLY__ */
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/*
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* kern_addr_valid() is (1) for FLATMEM and (0) for
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* SPARSEMEM and DISCONTIGMEM
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*/
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#ifdef CONFIG_FLATMEM
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#define kern_addr_valid(addr) (1)
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#else
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#define kern_addr_valid(kaddr) (0)
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#endif
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#endif /* _ASM_X86_PGTABLE_32_H */
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